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general description the max96706 is a compact deserializer especially suit - ed for automotive camera applications. features include adaptive equalization and an output crosspoint switch. an embedded control channel operates at 9.6kbps to 1mbps in uart, i 2 c, and mixed uart/i 2 c modes, allowing pro - gramming of serializer, deserializer (serdes), and camera registers, independent of video timing. the deserializer can track data from a spread- spectrum serial input. the serial input meets iso 10605 and iec 61000-4-2 esd standards. the core supply range is 1.7v to 1.9v and the i/o supply range is 1.7v to 3.6v. the device is available in a 32-pin (5mm x 5mm) tqfn package with 0.5mm lead pitch and operates over -40 c to +115 c temperature range. applications automotive camera applications benefts and features ideal for safety camera applications ? works with low-cost 50 coax (100 stp) cable ? error detection of video/control data ? high-immunity mode for robust control-channel emc tolerance ? retransmission of control data upon error ? best-in-class supply current: 190ma (max) ? adaptive equalization for 15m cable at full speed ? 32-pin (5mm x 5mm) tqfn package ? horizontal- and vertical-sync encoding and tracking high-speed deserialization for megapixel cameras ? up to 1.74gbps serial-bit rate ? 6.25mhz to 87mhz x 12-bit + h/v data ? 36.66mhz to 116mhz x 12-bit + h/v data (through internal encoding) multiple modes for system flexibility ? 9.6kbps to 1mbps control channel in uart, i 2 c (with clock stretch), or uart-to-i 2 c modes ? 2:1 input mux for camera selection ? 15 hardware-selectable i 2 c-device addresses ? pairs with any maxim gmsl serializer ? crosspoint switch maps data to any output reduces emi and shielding requirements ? spread-spectrum serial-input tracking and transfer to the parallel output ? 1.7v to 1.9v core and 1.7v to 3.6v i/o supply peripheral features for system verification ? built-in prbs receiver for ber testing ? eye-width monitor allows in-system test of high- speed serial link ? dedicated up/down gpi for camera frame sync trigger and other uses meets aec-q100 automotive specification ? -40c to +115c operating temperature range ? 8kv contact and 15kv air iec 61000-4-2 and iso 10605 esd protection ordering information appears at end of data sheet. 19-8248; rev 0; 4/16 simplifed block diagram cam max96705 max96706 video i 2 c gpu video i 2 c max96706 14-bit gmsl deserializer with coax or stp cable input evaluation kit available
maxim integrated 2 general description ............................................................................ 1 applications .................................................................................. 1 benefits and features .......................................................................... 1 simplified block diagram ........................................................................ 1 absolute maximum ratings ...................................................................... 6 package thermal characteristics ................................................................. 6 32-pin tqfn-ep ............................................................................. 6 dc electrical characteristics ..................................................................... 7 ac electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 typical operating characteristics ................................................................ 15 pin configuration ............................................................................. 16 pin description ............................................................................... 17 functional diagrams .......................................................................... 20 detailed description ........................................................................... 26 serial link signaling and data format ........................................................... 26 operating modes ......................................................................... 26 video/configuration link ................................................................... 26 single and double modes of operation ....................................................... 26 hs/vs encoding ......................................................................... 26 error detection ........................................................................... 26 bus widths .............................................................................. 27 control channel and register programming ...................................................... 30 forward control channel ................................................................... 30 reverse control channel ................................................................... 30 uart interface .......................................................................... 30 i 2 c interface ............................................................................ 30 remote-end operation .................................................................... 30 clock-stretch timing ...................................................................... 30 packet-based i 2 c ........................................................................ 30 packet protocol summary .................................................................. 31 control-channel error detection and packet retransmission .................................................................... 31 gpo/gpi control ........................................................................... 31 adaptive line equalizer ...................................................................... 31 eye-width monitor ........................................................................... 31 spread-spectrum tracking .................................................................... 31 cable-type configuration and input mux ........................................................ 31 crosspoint switch ........................................................................... 32 table of contents www.maximintegrated.com max96706 14-bit gmsl deserializer with coax or stp cable input
maxim integrated 3 shutdown/sleep modes ...................................................................... 32 configuration link ........................................................................ 32 serialization disable ...................................................................... 32 sleep mode ............................................................................. 32 power-down mode ........................................................................ 32 link-startup procedure ....................................................................... 32 register map ................................................................................ 34 applications information ........................................................................ 62 parallel interface ............................................................................ 62 bus data width .......................................................................... 62 bus data rates .......................................................................... 62 crossbar switch ............................................................................ 62 crossbar switch programming .............................................................. 62 recommended crossbar switch programming procedure ......................................... 62 control-channel interfaces .................................................................... 65 i 2 c .................................................................................... 65 i 2 c bit rate ............................................................................. 65 software programming of the device addresses ................................................ 65 i 2 c address translation .................................................................... 65 configuration blocking ..................................................................... 65 cascaded/parallel devices ................................................................. 65 dual c control .......................................................................... 65 packet-based control-channel i 2 c ........................................................... 65 uart .................................................................................. 66 base mode .............................................................................. 66 uart timing ............................................................................ 66 uart-to-i 2 c conversion ................................................................... 67 uart bypass mode ...................................................................... 68 device address .......................................................................... 68 cable equalizer ............................................................................. 68 errb output .............................................................................. 68 auto-error reset ......................................................................... 68 board layout ............................................................................... 69 power-supply circuits and bypassing ......................................................... 69 high-frequency signals .................................................................... 69 esd protection ............................................................................. 69 compatibility with other gmsl devices ......................................................... 69 device configuration and component selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 table of contents (continued) www.maximintegrated.com max96706 14-bit gmsl deserializer with coax or stp cable input
maxim integrated 4 internal input pulldowns .................................................................... 70 multifunction inputs ....................................................................... 70 i 2 c/uart pullup resistors ................................................................. 70 ac-coupling capacitors ................................................................... 70 cables and connectors .................................................................... 70 prbs ..................................................................................... 71 gpi/gpo .................................................................................. 71 fast detection of loss-of-lock .............................................................. 71 providing a frame sync (camera applications) ................................................. 71 entering/exiting sleep mode .................................................................. 71 legacy control channel ................................................................... 71 typical application circuit ...................................................................... 72 ordering information .......................................................................... 72 revision history .............................................................................. 73 figure 1. reverse control-channel output parameters ............................................... 21 figure 2. test circuit for differential input measurement .............................................. 22 figure 4. line fault ........................................................................... 22 figure 3. test circuit for single-ended input measurement ............................................ 22 figure 5. worst-case pattern output ............................................................. 23 figure 6. i 2 c timing parameters ................................................................. 23 figure 7. output rise-and-fall times ............................................................. 23 figure 8. deserializer delay ..................................................................... 24 figure 9. gpi-to-gpo delay .................................................................... 24 figure 10. lock time .......................................................................... 24 figure 11. power-up delay ..................................................................... 24 figure 12. active output to high-impedance time, high impedance to active-output time test circuit ......... 25 figure 13. active output to high-impedance time, high impedance to active-output time .................. 25 figure 14. 24-bit mode serial-data format ......................................................... 27 figure 15. 27-bit high-bandwidth mode serial-data format ........................................... 28 figure 16. 32-bit mode serial-data format ......................................................... 29 figure 17. coax connection ..................................................................... 31 figure 18. crosspoint-switch dataflow ............................................................ 32 figure 19. state diagram ....................................................................... 33 figure 20. gmsl-uart data format for base mode ................................................. 66 list of figures table of contents (continued) www.maximintegrated.com max96706 14-bit gmsl deserializer with coax or stp cable input
maxim integrated 5 figure 21. gmsl-uart protocol for base mode .................................................... 66 figure 22. sync byte (0x79) ..................................................................... 66 figure 23. ack byte (0xc3) ..................................................................... 66 figure 24. format conversion between gmsl uart and i 2 c with register address (i2cmethod = 0) ........ 67 figure 25. format conversion between gmsl uart and i 2 c with register address (i2cmethod = 1) ........ 67 figure 26. human body model esd test circuit ..................................................... 69 figure 27. iec 61000-4-2 contact discharge esd test circuit ......................................... 69 figure 28. iso 10605 contact discharge esd test circuit ............................................ 69 table 1. reverse control-channel modes .......................................................... 30 table 2. link-startup procedure ................................................................. 33 table 3. output-data width selection ............................................................. 62 table 4. data-rate selection table ............................................................... 62 table 5. output map (dbl = 0 or dbl = 1, first word) ............................................... 63 table 6. output map (dbl = 1, second word) ...................................................... 64 table 7. legend .............................................................................. 64 table 8. default-device address ................................................................. 68 table 9. cable-equalizer boost levels ............................................................ 68 table 10. feature compatibility .................................................................. 70 table 11. suggested connectors and cables for gmsl ............................................... 71 list of tables list of figures (continued) www.maximintegrated.com max96706 14-bit gmsl deserializer with coax or stp cable input
avdd to ep* ........................................................ -0.5v to +1.9v dvdd to ep* ........................................................ -0.5v to +1.9v iovdd to ep* ....................................................... -0.5v to +3.9v lmn_ to ep* (15ma current limit) ........................ -0.5v to +3.9v in_+, in_- to ep* .................................................. -0.5v to +1.9v all other pins to ep* ......................... -0.5v to (iovdd + 0.5v)v in_+, in_- short circuit to ground or supply ........... continuous operating temperature range .......................... -40c to +115c junction temperature ...................................................... +125c storage temperature range ............................ -40c to +150c soldering temperature (reflow) ....................................... +260c continuous power dissipation t a = +70c, 32-pin tqfn (derate 34.5 mw/c above +70c.) ...................... 2758.6mw *ep connected to ic ground. for the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages . note that a +, #, or - in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. 32-pin tqfn-ep package code t3255+8 outline number 21-0140 land pattern number 90-0013 thermal resistance, single layer board: junction-to-ambient ( ja ) 47 junction-to-case thermal resistance ( jc ) 1.7 thermal resistance, four layer board: junction-to-ambient ( ja ) 29 junction-to-case thermal resistance ( jc ) 1.7 maxim integrated 6 absolute maximum ratings stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to ab solute maximum rating conditions for extended periods may affect device reliability. package thermal characteristics package thermal resistances were obtained using the method described in jedec specification jesd51-7, using a four-layer board. for detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial . www.maximintegrated.com max96706 14-bit gmsl deserializer with coax or stp cable input
(v dvdd = v avdd = 1.7 to 1.9v, v iovdd = 1.7v to 3.6v, r l = 100 1% (differential), ep connected to pcb ground, t a = -40c to +115c, typical values are at, v dvdd = v avdd = v iovdd = 1.8v, t a = +25c, unless otherwise noted.) (note 1) dc electrical characteristics parameter symbol conditions min typ max units single-ended inputs (gpi, cxtp, i2csel, add_, him, pwdnb, ms) high-level input voltage v ih1 0.65 x v iovdd v low-level input voltage v il1 0.35 x v iovdd v input current i in1 v in = 0 to v iovdd -20 20 a single-ended outputs (dout_, vs, hs, de, pclkout) high-level output voltage v oh1 i oh = -2ma, dcs = 0 v iovdd - 0.3 v i oh = -2ma, dcs = 1 v iovdd - 0.2 low-level output voltage v ol1 i ol = 2ma, dcs = 0 0.3 v i ol = 2ma, dcs = 1 0.2 high-impedance output current i oz outenb = 1, v out = 0v or v iovdd -20 20 a output short-circuit current i os dout_, v o = 0v, dcs = 0, v iovdd = 3.0v to 3.6v 15 25 39 ma dout_, v o = 0v, dcs = 0, v iovdd = 1.7v to 1.9v 3 7 13 dout_, v o = 0v, dcs = 1, v iovdd = 3.0v to 3.6v 20 35 63 dout_, v o = 0v, dcs = 1, v iovdd = 1.7v to 1.9v 5 10 21 pclkout_, v o = 0v, dcs = 0, v iovdd = 3.0v to 3.6v 15 33 50 pclkout_, v o = 0v, dcs = 0, v iovdd = 1.7v to 1.9v 5 10 17 pclkout_, v o = 0v, dcs = 1, v iovdd = 3.0v to 3.6v 30 54 97 pclkout_, v o = 0v, dcs = 1, v iovdd = 1.7v to 1.9v 9 16 32 maxim integrated 7 www.maximintegrated.com max96706 14-bit gmsl deserializer with coax or stp cable input
(v dvdd = v avdd = 1.7 to 1.9v, v iovdd = 1.7v to 3.6v, r l = 100 1% (differential), ep connected to pcb ground, t a = -40c to +115c, typical values are at, v dvdd = v avdd = v iovdd = 1.8v, t a = +25c, unless otherwise noted.) (note 1) parameter symbol conditions min typ max units uart/i 2 c and general-purpose i/os (rx/sda, tx/scl, gpio_, errb, lock, lfl tb) with open-drain outputs high-level input voltage v ih2 0.7 x v iovdd v low-level input voltage v il2 0.3 x v iovdd v input current i in2 v in = 0 to v iovdd (note 2), rx/sda, tx/scl -110 5 a i in v in = 0 to v iovdd (note 2), gpio_, errb, lock -80 5 low-level open-drain output voltage v ol i ol = 3ma, v iovdd = 1.7v to 1.9v 0.4 v i ol = 3ma, v iovdd = 3.0v to 3.6v 0.3 input capacitance c in each pin (note 3) 10 pf outputs for reverse control channel (in0+, in0-, in1+, in1-) differential high-output peak voltage (v in+ - v in- ) v rodh forward channel disabled, normal-immunity mode ( figure 1 ) 30 60 mv forward channel disabled, high-immunity mode ( figure 1 ) 50 100 differential low-output peak voltage (v in+ - v in- ) v rodl forward channel disabled, normal-immunity mode ( figure 1 ) -60 -30 mv forward channel disabled, high-immunity mode ( figure 1 ) -100 -50 single-ended high-output peak voltage v rosh forward channel disabled, normal-immunity mode ( figure 1 ) 30 60 mv forward channel disabled, high-immunity mode ( figure 1 ) 50 100 single-ended low-output peak voltage v rosl forward channel disabled, normal-immunity mode ( figure 1 ) -60 -30 mv forward channel disabled, high-immunity mode ( figure 1 ) -100 -50 maxim integrated 8 dc electrical characteristics (continued) www.maximintegrated.com max96706 14-bit gmsl deserializer with coax or stp cable input
(v dvdd = v avdd = 1.7 to 1.9v, v iovdd = 1.7v to 3.6v, r l = 100 1% (differential), ep connected to pcb ground, t a = -40c to +115c, typical values are at, v dvdd = v avdd = v iovdd = 1.8v, t a = +25c, unless otherwise noted.) (note 1) parameter symbol conditions min typ max units differential inputs (in0+, in0-, in1+, in1-) differential high-input threshold peak voltage (v in+ - v in- ) v idh(p) activity detector, medium threshold (0x22 d[6:5] = 01) ( figure 2 ) 60 mv activity detector, low threshold (0x22 d[6:5] = 00) ( figure 2 ) 49 differential low-input threshold peak voltage (v in+ - v in- ) v idl(p) activity detector, medium threshold (0x22 d[6:5] = 01) ( figure 2 ) -60 mv activity detector, low threshold (0x22 d[6:5] = 00) ( figure 2 ) -49 input common-mode voltage (v in+ + v in- )/2 v cmr 1 1.3 1.6 v differential-input resistance (internal) r i 80 100 130 single-ended inputs (in0+, in0-, in1+, in1-) single-ended high-input threshold peak voltage v ish(p) activity detector, medium threshold (0x22 d[6:5] = 01) ( figure 3 ) 43 mv activity detector, low threshold (0x22 d[6:5] = 00) ( figure 3 ) 33 single-ended low-input threshold peak voltage v isl(p) activity detector, medium threshold (0x22 d[6:5] = 01) ( figure 3 ) -43 mv activity detector, low threshold (0x22 d[6:5] = 00) ( figure 3 ) -33 input resistance (internal) r i 40 50 65 line fault detection inputs (lmn0, lmn1) short-to-ground threshold v tg ( figure 4 ) 0.3 v normal threshold v tn ( figure 4 ) 0.57 1.07 v open threshold v to ( figure 4 ) 1.45 v io + 0.06 v open-input voltage v io ( figure 4 ) 1.47 1.75 v short-to-battery threshold v te ( figure 4 ) 2.47 v maxim integrated 9 dc electrical characteristics (continued) www.maximintegrated.com max96706 14-bit gmsl deserializer with coax or stp cable input
(v dvdd = v avdd = 1.7 to 1.9v, v iovdd = 1.7v to 3.6v, r l = 100 1% (differential), ep connected to pcb ground, t a = -40c to +115c, typical values are at, v dvdd = v avdd = v iovdd = 1.8v, t a = +25c, unless otherwise noted.) (note 1) parameter symbol conditions min typ max units power supply worst-case supply current ( figure 5 ) i wcs f pclkout = 116mhz, hibw = 1, bws = 0, double output, avdd + dvdd (1.9v) 100 120 ma f pclkout = 116mhz, hibw = 0, bws = 0, double output, avdd + dvdd (1.9v) 95 115 f pclkout = 116mhz, bws = 0, double output, iovdd (1.9v) c l = 5pf (dcs = 0) (note 3) 22 25 f pclkout = 116mhz, bws = 0, double output, iovdd (1.9v), c l = 10pf (dcs = 1) (note 3) 31 35 f pclkout = 116mhz, bws = 0, double output, iovdd (3.6v), c l = 5pf (dcs = 0) (note 3) 44 49 f pclkout = 116mhz, bws = 0, double output, iovdd (3.6v), c l = 10pf (dcs = 1) (note 3) 63 70 f pclkout = 87mhz, bws = 1, double output, iovdd (1.9v), avdd + dvdd (1.9v) 95 115 f pclkout = 87mhz, bws = 1, double output, iovdd (1.9v), c l = 5pf (dcs = 0) (note 3) 17 19 f pclkout = 87mhz, bws = 1, double output, iovdd (1.9v), c l = 10pf (dcs = 1) (note 3) 24 27 f pclkout = 87mhz, bws = 1, double output, iovdd (3.6v), c l = 5pf (dcs = 0) (note 3) 33 36 f pclkout = 87mhz, bws = 1, double output, iovdd (3.6v), c l = 10pf (dcs = 1) (note 3) 44 49 f pclkout = 58mhz, hibw = 1, bws = 0, single output, avdd + dvdd (1.9v) 70 84 f pclkout = 58mhz, hibw = 0, bws = 0, single output, avdd + dvdd (1.9v) 70 84 f pclkout = 58mhz, bws = 0, single output, iovdd (1.9v), c l = 5pf (dcs = 0) (note 3) 11 13 f pclkout = 58mhz, bws = 0, single output, iovdd (3.6v), c l = 10pf (dcs = 1) (note 3) 15 18 maxim integrated 10 dc electrical characteristics (continued) www.maximintegrated.com max96706 14-bit gmsl deserializer with coax or stp cable input
parameter symbol conditions min typ max units power supply (continued) worst-case supply current ( figure 5 ) (continued) i wcs f pclkout = 58mhz, bws = 0, single output, iovdd (3.6v), c l = 5pf (dcs = 0) (note 3) 22 25 ma f pclkout = 58mhz, bws = 0, single output, iovdd (3.6v), c l = 10pf (dcs = 1) (note 3) 30 34 f pclkout = 43.5mhz, bws = 1, single output, avdd + dvdd (1.9v) 70 84 f pclkout = 43.5mhz, bws = 1, single output, iovdd (1.9v), c l = 5pf (dcs = 0) (note 3) 8 10 f pclkout = 43.5mhz, bws = 1, single output, iovdd (1.9v), c l = 10pf (dcs = 1) (note 3) 12 14 f pclkout = 43.5mhz, bws = 1, single output, iovdd (3.6v), c l = 5pf (dcs = 0) (note 3) 16 18 f pclkout = 43.5mhz, bws = 1, single output, iovdd (3.6v), c l = 10pf (dcs = 1) (note 3) 22 25 sleep-mode supply current i ccs wake-up receivers enabled 54 160 a wake-up receivers disabled 15 100 power-down supply current i ccz pwdnb = low 15 100 a esd protection in+, in- (note 4) v esd human body model, r d = 1.5k, c s = 100pf 8 kv iec 61000-4-2, r d = 330, c s = 150pf, contact discharge 10 iec 61000-4-2, r d = 330, c s = 150pf, air discharge 15 iso 10605, r d = 2k, c s = 330pf, contact discharge 10 iso 10605, r d = 2k, c s = 330pf, air discharge 30 all other pins (note 5) v esd human body model, r d = 1.5k, c s = 100pf 4 kv machine model 250 v maxim integrated 11 (v dvdd = v avdd = 1.7 to 1.9v, v iovdd = 1.7v to 3.6v, r l = 100 1% (differential), ep connected to pcb ground, t a = -40c to +115c, typical values are at, v dvdd = v avdd = v iovdd = 1.8v, t a = +25c, unless otherwise noted.) (note 1) dc electrical characteristics (continued) www.maximintegrated.com max96706 14-bit gmsl deserializer with coax or stp cable input
(v dvdd = v avdd = 1.7 to 1.9v, v iovdd = 1.7v to 3.6v, r l = 100 1% (differential), ep connected to pcb ground, t a = -40c to +115c, typical values are at, v dvdd = v avdd = v iovdd = 1.8v, t a = +25c, unless otherwise noted.) (note 1) parameter symbol conditions min typ max units parallel clock output (pclkout) clock frequency f pclkout bws = 1, drs = 1, single output 6.25 12.5 mhz bws = 0, drs = 1, single output 8.33 16.66 bws = 1, drs = 0, single output 12.5 43.5 bws = 0, hibw = 0, drs = 0, single output 16.66 58 bws = 0, hibw = 1, drs = 0, single output 36.66 58 bws = 1, drs = 0, double output 25 87 bws = 0, hibw = 0, drs = 0, double output 33.33 116 bws = 0, hibw = 1, drs = 0, double output 73.33 116 data valid before clock t dvb pclkout and dout_, dcs = 1, c l = 10pf or dcs = 0, c l = 5pf, nonstaggered dout_ 0.4t 0.5t ns pclkout and dout_, dcs = 1, c l = 10pf or dcs = 0, c l = 5pf, staggered dout_ 0.35t 0.4t data valid after clock t dva pclkout and dout_, dcs = 1, c l = 10pf or dcs = 0, c l = 5pf, nonstaggered dout_ 0.35t 0.4t ns pclkout and dout_, dcs = 1, c l = 10pf or dcs = 0, c l = 5pf, staggered dout_ 0.3t 0.35t clock jitter t j rms period jitter, spread off, 1.74gbps prbs pattern, ui = 1/f pclkout, dbl = 1, double output) 0.05 ui period jitter; peak-to-peak, spread off, 1.74gbps, prbs pattern, ui = 1/f pclkout, dbl = 0, single output) 0.01 i 2 c/uart port timing i 2 c/uart bit rate 9.6 1000 kbps output rise time t r 30% to 70%, c l = 10pf to 100pf, 1k pullup to iovdd 20 150 ns output fall time t f 70% to 30%, c l = 10pf to 100pf, 1k pullup to iovdd 20 150 ns maxim integrated 12 ac electrical characteristics www.maximintegrated.com max96706 14-bit gmsl deserializer with coax or stp cable input
(v dvdd = v avdd = 1.7 to 1.9v, v iovdd = 1.7v to 3.6v, r l = 100 1% (differential), ep connected to pcb ground, t a = -40c to +115c, typical values are at, v dvdd = v avdd = v iovdd = 1.8v, t a = +25c, unless otherwise noted.) (note 1) parameter symbol conditions min typ max units i 2 c timing ( figure 6 ) scl clock frequency f scl low f scl range: (i2cmstbt = 010, i2cslvsh = 10) 9.6 100 khz mid f scl range: (i2cmstbt 101, i2cslvsh = 01) >100 400 high f scl range: (i2cmstbt = 111, i2cslvsh = 00) >400 1000 start condition hold time t hd:sta f scl range, low 4 s f scl range, mid 0.6 f scl range, high 0.26 low period of scl clock t low f scl range, low 4.7 s f scl range, mid 1.3 f scl range, high 0.5 high period of scl clock t high f scl range, low 4 s f scl range, mid 0.6 f scl range, high 0.26 repeated start condition setup time t su:sta f scl range, low 4.7 s f scl range, mid 0.6 f scl range, high 0.26 data hold time t hd:dat f scl range, low 0 ns f scl range, mid 0 f scl range, high 0 data setup time t su:dat f scl range, low 250 ns f scl range, mid 100 f scl range, high 50 setup time for stop condition t su:sto f scl range, low 4 s f scl range, mid 0.6 f scl range, high 0.26 bus free time t buf f scl range, low 4.7 s f scl range, mid 1.3 f scl range, high 0.5 data valid time t vd:dat f scl range, low 3.45 s f scl range, mid 0.9 f scl range, high 0.45 data valid acknowledge time t vd:ack f scl range, low 3.45 s f scl range, mid 0.9 f scl range, high 0.45 pulse width of spikes suppressed t sp f scl range, low 50 ns f scl range, mid 50 f scl range, high 50 maxim integrated 13 ac electrical characteristics (continued) www.maximintegrated.com max96706 14-bit gmsl deserializer with coax or stp cable input
(v dvdd = v avdd = 1.7 to 1.9v, v iovdd = 1.7v to 3.6v, r l = 100 1% (differential), ep connected to pcb ground, t a = -40c to +115c, typical values are at, v dvdd = v avdd = v iovdd = 1.8v, t a = +25c, unless otherwise noted.) (note 1) note 1: limits are 100% production tested at t a = +115c. limits over the operating temperature range are guaranteed by design and characterization, unless otherwise noted. note 2: i in min is due to voltage drop across the internal pullup resistor. note 3: not production tested. guaranteed by design. note 4: specified pin to ground . note 5: specified pin to all supply/ground . note 6: measured in serial link bit times. bit time = 1/(30 x f pclkout ) for bws = gnd. bit time = 1/(40 x f pclkout ) for bws = 1. parameter symbol conditions min typ max units capacitive load each bus line c b 100 pf switching characteristics (note 3) pclkout rise-and-fall time ( figure 7 ) t r, t f 20% to 80%, v iovdd = 1.7v to 1.9v, dcs = 1, c l = 10pf 0.4 2.2 ns 20% to 80%, v iovdd = 1.7v to 1.9v, dcs = 0, c l = 5pf 0.5 2.8 20% to 80%, v iovdd = 3.0v to 3.6v, dcs = 1, c l = 10pf 0.25 1.8 20% to 80%, v iovdd = 3.0v to 3.6v, dcs = 0, c l = 5pf 0.3 2 parallel data rise-and-fall time ( figure 7 ) t r, t f 20% to 80%, v iovdd = 1.7v to 1.9v, dcs = 1, c l = 10pf 0.5 3.1 ns 20% to 80%, v iovdd = 1.7v to 1.9v, dcs = 0, c l = 5pf 0.6 3.8 20% to 80%, v iovdd = 3.0v to 3.6v, dcs = 1, c l = 10pf 0.3 2.2 20% to 80%, v iovdd = 3.0v to 3.6v, dcs = 0, c l = 5pf 0.4 2.4 deserializer delay t sd ( figure 8 ) (note 6) 2160 bits reverse control-channel output rise time t r no forward-channel data transmission 180 400 ns reverse control-channel output fall time t f no forward-channel data transmission 180 400 ns gpi-to-gpo delay t gpio deserializer gpi to serializer gpo ( figure 9 ) 350 s lock time (note 3) t lock ( figure 10 ) aeq on, packet cc off 1.6 ms ( figure 10 ) aeq on, packet cc on 4.1 ( figure 10 ) aeq off, packet cc off 1 ( figure 10 ) aeq off, packet cc on 3.5 power-up time t pu ( figure 11 ) 6.5 ms active output to high-imped - ance time t oaz ( figure 12 , figure 13 ) cc write outenb =1 250 ns active high-impedance to output time t oza ( figure 12 , figure 13 ) cc write outenb =0 250 ns maxim integrated 14 ac electrical characteristics (continued) www.maximintegrated.com max96706 14-bit gmsl deserializer with coax or stp cable input
(v avdd = v dvdd = v iovdd = 1.8v, t a = +25c, unless otherwise noted.) maxim integrated 15 typical operating characteristics 40 50 60 70 80 90 100 15 35 55 75 95 115 supply current (ma) pixel clock frequency (mhz) supply current vs. pixel clock frequency (bws = 0, hibw = 0) toc01 prbs on, coax mode eq off eq on dbl = 1 dbl = 0 40 50 60 70 80 90 100 10 30 50 70 90 supply current (ma) pixel clock frequency (mhz) supply current vs. pixel clock frequency (bws = 1, hibw = 0) toc03 prbs on, coax mode eq off eq on dbl = 1 dbl = 0 0 10 20 30 40 50 60 70 0 10 20 30 40 pixel clock frequency (mhz) coax cable length (m) maximum pixel clock frequency vs. coax cable length (ber < 10 - 10 ) toc05 ber can be as low as 10 - 12 for cable lengths less than 15m aeq no eq 4.3db eq no pe, dbl = 0 40 50 60 70 80 90 100 15 35 55 75 95 115 supply current (ma) pixel clock frequency (mhz) supply current vs. pixel clock frequency (bws = 0, hibw = 1) toc02 prbs on, coax mode eq off eq off dbl = 1 dbl = 0 0 10 20 30 40 50 60 70 0 5 10 15 20 25 pixel clock frequency (mhz) stp cable length (m) maximum pixel clock frequency vs. stp cable length (ber < 10 - 10 ) toc04 ber can be as low as 10 - 12 for cable lengths less than 15m aeq no eq 4.3db eq 9.7db eq no pe, dbl = 0 www.maximintegrated.com max96706 14-bit gmsl deserializer with coax or stp cable input
maxim integrated 16 max96706 tqfn (5mm x 5mm) top view lmn1 in1- avdd in0+ in0- gpi dout6/add0 pclkout dout7/add1 dout5/him dout8/add2 dout9/add3 1 2 lfltb 4 5 6 7 dout2 dout1 dout13/vs dvdd lock errb in1+ iovdd 3 dout0 tx/scl ms rx/sda + pwdnb dout12/hs dout3 dout11/cxtp/de lmn0 dout10/i2csel 8 dout4 16 15 14 13 12 11 10 9 17 18 19 20 21 22 23 24 26 25 27 28 29 30 31 32 pin confguration www.maximintegrated.com max96706 14-bit gmsl deserializer with coax or stp cable input
pin name function ref supply type power 5 avdd 1.8v analog power supply. bypass avdd to ep with 0.1f and 0.001f capacitors placed as close as possible to the device, with the smaller-value capacitor closest to avdd. power 13 dvdd 1.8v digital power supply. bypass dvdd to ep with 0.1f and 0.001f capacitors placed as close as possible to the device, with the smaller-value capacitor closest to dvdd. power 22 iovdd i/o supply voltage. 1.8v to 3.3v logic i/o power supply. bypass iovdd to ep with 0.1f and 0.001f capacitors placed as close as possible to the device, with the smaller-value capacitor closest to iovdd. power ep exposed pad. ep is internally connected to device ground. must connect ep to the pcb ground plane through a via array for proper thermal and electrical performance. power high-speed digital high-speed digital / multifunction 14 dout13/vs parallel-data/vertical-sync output. defaults to parallel-data output on power-up. vertical-sync output when hs/vs encoding is enabled, or when in high-bandwidth mode. iovdd digital 15 dout12/hs parallel-data/horizontal-sync output. defaults to parallel-data output on power-up. horizontal-sync output when hs/vs encoding is enabled, or when in high-bandwidth mode. iovdd digital 16 dout11/ cxtp/de parallel-data output/cable-type input/data-enable output with internal pulldown to ep. cx/tp is latched at power-up, or when resuming from power-down mode (pwdnb = low), and switches to parallel/data-enable output after power-up. connect cxtp to iovdd with a 30k? resistor to set high (coax mode), or leave open to set low (twisted-pair mode). data-enable output when hibw = 1. iovdd digital 17 dout10/ i2csel parallel-data output/i 2 c-select input with internal pulldown to ep. i2csel is latched at power-up, or when resuming from power- down mode (pwdnb = low), and switches to parallel-data output after power-up. connect i2csel to iovdd with a 30k? resistor to set high (i 2 c interface), or leave open to set low (uart interface). iovdd digital 18 dout9/ add3 parallel-data output/address input with internal pulldown to ep. add3 is latched at power-up, or when resuming from power-down mode (pwdnb = low), and switches to parallel-data output after power-up. connect add3 to iovdd with a 30k? resistor to set high, or leave open to set low. iovdd digital 19 dout8/ add2 parallel-data output/address input with internal pulldown to ep. add2 is latched at power-up, or when resuming from power-down mode (pwdnb = low), and switches to parallel-data output after power-up. connect add2 to iovdd with a 30k? resistor to set high, or leave open to set low. iovdd digital maxim integrated 17 pin description www.maximintegrated.com max96706 14-bit gmsl deserializer with coax or stp cable input
pin name function ref supply type 20 dout7/ add1 parallel-data output/address input with internal pulldown to ep. add1 is latched at power-up, or when resuming from power-down mode (pwdnb = low), and switches to parallel-data output after power-up. connect add1 to iovdd with a 30k? resistor to set high, or leave open to set low. iovdd digital 23 dout6/ add0 parallel-data output/address input with internal pulldown to ep. add0 is latched at power-up, or when resuming from power-down mode (pwdnb = low), and switches to parallel-data output after power-up. connect add0 to iovdd with a 30k? resistor to set high, or leave open to set low. iovdd digital 24 dout5/him parallel-data output/high-immunity mode input with internal pulldown to ep. him input latched at power-up, or when resuming from power-down mode (pwdnb = low), and switches to parallel- data output after power-up. connect him to iovdd with a 30k? resistor to set high, or leave open to set low. highimm in the serializer must be set to the same value. iovdd digital high-speed digital / single-function 21 pclkout parallel-clock output. provides timing signal to latch parallel-data outputs to the input of another device. iovdd digital 25 dout4 parallel-data output iovdd digital 26 dout3 parallel-data output iovdd digital 29 dout2 parallel-data output iovdd digital 30 dout1 parallel-data output iovdd digital 31 dout0 parallel-data output iovdd digital line fault 2 lmn1 line-fault monitor input 1 (see figure 4 ) analog 8 lmn0 line-fault monitor input 0 ) (see figure 4 ) analog 28 lfltb line-fault output. lfltb is active low, and has a 60k? internal pullup to iovdd. lfltb low indicates a line-fault condition at lmn0, or lmn1. lfltb is output high when pwdnb is low. iovdd digital maxim integrated 18 pin description (continued) www.maximintegrated.com max96706 14-bit gmsl deserializer with coax or stp cable input
pin name function ref supply type other pins 1 gpi general-purpose input with internal pulldown to ep. serializer gpo (or int) output follows the state of the gpi. iovdd digital 3 in1+ noninverting cml serial-data input 1. coax input when cxtp is high. 4 in1- inverting cml serial-data input 1 6 in0+ noninverting cml serial-data input 0. coax input when cxtp is high. 7 in0- inverting cml serial-data input 0 9 rx/sda receive/serial data. input/output with internal 30k? pullup to iovdd. in uart mode, rx/sda is the rx input of the serializer's uart. in i 2 c mode, rx/sda is the sda input/output of the serial - izer's i 2 c master/slave. rx/sda has an open-drain driver and requires a pullup resistor. iovdd digital 10 tx/scl transmit/serial clock. input/output with internal 30k? pullup to iovdd. in uart mode, tx/scl is the tx output of the serializer's uart. in i 2 c mode, tx/scl is the scl input/output of the serial - izer's i 2 c master/slave. tx/scl has an open-drain driver and requires a pullup resistor. iovdd digital 11 errb error output. active-low, open-drain video data error output with internal pullup to iovdd. errb goes low when decoding errors during normal operation exceed a programmed threshold, or when at least one prbs error is detected during a prbs test. errb is output high when pwdnb is low. iovdd digital 12 lock lock output. open-drain output with internal pullup to iovdd. lock high indicates plls are locked with correct serial-word boundary alignment. lock low indicates plls are not locked, or incorrect serial-word boundary alignment. lock is low when the confguration link is active. lock is output high when pwdnb is low. iovdd digital 27 pwdnb active-low, power-down input with internal pulldown to ep. set pwdnb low to enter power-down mode to reduce power consumption. iovdd digital 32 ms mode-select input with internal pulldown to ep. set ms low to select base mode. set ms high to select bypass mode. iovdd digital maxim integrated 19 pin description (continued) www.maximintegrated.com max96706 14-bit gmsl deserializer with coax or stp cable input
maxim integrated 20 functional diagrams serial to parallel cdr/pll descramble/ hven/crc/ parity/ decode/dbl control fcc pclkout reverse control channel max96706 in0+ in0- clkdiv dout[4:0] tx uart/i 2 c tx/ scl rx/ sda gpi 14 x 14 crossbar switch sync video adaptive eq in1+ in1- dout5/him dout6/add0 dout7/add1 dout8/add2 dout9/add3 dout10/i2csel dout11/cx/tp/de dout12/hs dout13/vs him add0 add1 add2 add3 i2csel cx/tp pwdnb him add[3:0] i2csel cx/tp errb lock line fault lmn0 lmn1 lfltb eye-width monitor cml rx cml rx www.maximintegrated.com max96706 14-bit gmsl deserializer with coax or stp cable input
figure 1. reverse control-channel output parameters maxim integrated 21 gmsl deserializer reverse control-channel transmitter in+ in- in- in+ in+ in- v od r l /2 r l /2 v cmr v cmr v roh (in+) - (in-) t r 0.1 x v rol 0.9 x v rol t f v rol 0.9 x v roh 0.1 x v roh www.maximintegrated.com max96706 14-bit gmsl deserializer with coax or stp cable input
figure 2. test circuit for differential input measurement figure 3. test circuit for single-ended input measurement figure 4. line fault maxim integrated 22 v in+ r l /2 r l /2 c in c in v id(p) in+ in- v id(p) = | v in+ - v in- | v cmr = (v in+ + v in- )/2 v in- _ + _ _ + c in 0 . 22 f 49 . 9 ? + - v in _ in _ v is ( p ) output logic (in+) output logic (in-) reference voltage generator gmsl deserializer gmsl deserializer twisted pair connectors *1% tolerance lfltb lmn0 1.8v lmn1 49.9k?* 49.9k?* lmn1 in+ in- 4.99k?* 45.3k?* 45.3k?* 4.99k?* lmn0 gmsl deserializer coax connectors 1.8v 49.9k?* in+ in- 45.3k?* lmn0 4.99k?* 49.9?* www.maximintegrated.com max96706 14-bit gmsl deserializer with coax or stp cable input
figure 7. output rise-and-fall times figure 5. worst-case pattern output figure 6. i 2 c timing parameters maxim integrated 23 0.8 x v i0vdd 0.2 x v i0vdd t f t r c l single-ended output load protocol scl sda start condition (s) bit 7 msb (a7) bit 6 (a6) bit 0 (r/w) acknowledge (a) stop condition (p) v iovdd x 0.7 v iovdd x 0.3 v iovdd x 0.7 v iovdd x 0.3 t su;sta t low t high t buf t hd;sta t r t sp t f t su;dat t hd;dat t vd;dat t vd;ack t su;sto 1/f scl pclkout dout_ note: pclkout programmed for rising latch edge. www.maximintegrated.com max96706 14-bit gmsl deserializer with coax or stp cable input
figure 8. deserializer delay figure 9. gpi-to-gpo delay figure 10. lock time figure 11. power-up delay maxim integrated 24 first bit in+/- dout_ pclkout last bit serial word n serial-word length serial word n+1 serial word n+2 t sd parallel word n-2 parallel word n-1 parallel word n note: pclkout programmed for rising latching edge. t gpio t gpio v oh_min v ol_max v ih_min v il_max deserializer gpi serializer gpo in+/- lock t pu pwdn v oh v ih1 in+ - in- lock t lock pwdn must be high v oh www.maximintegrated.com max96706 14-bit gmsl deserializer with coax or stp cable input
figure 12. active output to high-impedance time, high impedance to active-output time test circuit figure 13. active output to high-impedance time, high impedance to active-output time maxim integrated 25 rx / sda disable packet enable packet 0.9 x v iovdd 0.1 x v iovdd dout_ t oaz t oaz uart/i2c c l rs/sda 5ki dout_ max96706 v iovdd www.maximintegrated.com max96706 14-bit gmsl deserializer with coax or stp cable input
detailed description the max96706 deserializer is a compact device with features especially suited for automotive camera applications. the device operates at a variety of output widths and word rates up to a total serial-data rate up to 1.75gbps. high-bandwidth mode offers a 116mhz parallel clock rate with 12 bits of video data + 2 bits of sync (hs/vs) data. an embedded 9.6kbps to 1mbps control channel programs the serializer, deserializer, and any attached uart or i 2 c peripherals. to promote safety applications, the device features crc protection of video and control data. in addition, control-channel retransmission and high-immunity modes reduce the effects of bit errors corrupting communica - tion. automatic equalization, along with a prbs tester and an embedded eye-width monitor, allow for in-system optimization of the link. this device operates over the -40c to +115c automo - tive temperature range. serial link signaling and data format the serializer scrambles the input parallel data and combines this with the forward control data. the data is then encoded for transmission and output as a single bitstream at several times the input word rate (depending on bus width). the deserializer receives the serial data and recovers the clock signal. the data is then deserial - ized, decoded, and descrambled into parallel output data and forward control data. operating modes the gmsl devices are configurable to operate in many modes, depending on the application. these modes allow for a more efficient use of serial bandwidth. most of these settings are set during system design and are configured using the external configuration pins, or through register bits. video/confguration link in normal operation, the serializer runs in video-link mode (seren = 1) with video data and control data sent across the serial link. set seren = 0 in the serializer to turn off serialization. the serializer powers up in video-link mode, and requires a valid pclk for operation. the configuration link is available to set up the serializer, deserializer, and peripherals when pclk is not available. set seren = 0 and clink = 1 in the serializer to enable the configuration link (seren = 1 forces the serializer into video-link mode). once pclk has been established, turn on the video link (seren = 1). by default, video-link mode requires a valid pclk for opera - tion. set auto_clink bit = 1 (if supported), and seren = 1 in the serializer to automatically switch between the video link and configuration link whenever pclk is not present. single and double modes of operation single-/double-mode operation configures the available 1.74gbps bandwidth into a variety of widths and word rates. single-mode operation is compatible with all gmsl devices, and serializes one parallel word for each serial word. double mode serializes two half-width parallel words for each serial word, and results in a 2x increase in parallel word-rate range (compared to single mode). set dbl = 0 for single-mode operation and dbl = 1 for double-mode operation. hs/vs encoding by default, gmsl assigns a video bit slot to hsync, vsync, and de (if used). with hs/vs encoding, the device instead encodes special packets to sync signals to free up additional video bit slots. hs/vs encoding is on by default when the device is in high-bandwidth mode. (hibw = 1). de is encoded only when hibw = 1 and de_en = 1. set hven = 1 to turn on hs/vs encoding when hibw = 0 (de, if enabled uses up a video bit). hs/vs encoding requires that hsync, vsync, and de (if used) remain high during the active video, and low during the blanking period. use hs/vs inversion when using reverse-polarity sync signals. error detection the serial link's 8b/10b encoding/decoding, and 1-bit parity detect bit errors that occur on the serial link. an optional 6-bit crc check is available at the expense of 6 video bits (when hibw = 0). to activate 6-bit crc mode, set pxl_crc = 1 in the remote-side device first, and then in the local-side device. when using 6-bit crc mode, the available internal bus width is reduced by 6 bits in single- input mode (dbl = 0) and 3 bits in double-input mode (dbl = 1). note that the input bus width may already have been reduced due to pin availability of the serializer or deserializer; thus, the reduction of bandwidth from crc may not be visible (see table 3 ). an additional 32-bit video line crc is available by setting line_crc_en = 1. when enabled, the serializer calculates the 32-bit crc of the video line and sends this information during the blanking period. the deserializer compares the received crc with the video line data. the deserializer's line_crc_err bit latches when a crc error is detected. line_crc_err clears when read. maxim integrated 26 www.maximintegrated.com max96706 14-bit gmsl deserializer with coax or stp cable input
bus widths the serial link has multiple bus-width settings that determine the parallel bus width and the resulting parallel word rate. the serial link operates to a maximum serial bit rate of 1.74gbps. the bws bit determines if each serial packet is 30 or 40 bits long, which translates to a maximum serial packet rate; thus, a maximum parallel word rate of 58mhz or 43.5mhz when bws = 0 or 1, respectively. decoding translates the 30- or 40-bit serial packets into 24, 27, or 32 parallel bits. one bit is used for parity, while a second is reserved for the control channel. an additional 6 bits is used during optional 6-bit crc. in addition, double mode splits the remaining word size in half if used. the remaining bits can be used for video bits minus any sync bits if hv encoding is not used. note: the following modes list the internal bus widths. the number of available input and output pins may limit the actual bus width available. 24-bit mode ( figure 14 ) when bws = 0 and hibw = 0, the 30-bit serial packet corresponds with three 8b/10b symbols, representing 24 bits (24-bit mode). after parity and control channel, this leaves 16/22 bits of video data if crc is/is not used (single mode), or 8/11 bits of video data if crc is/is not used (double mode). figure 14. 24-bit mode serial-data format maxim integrated 27 24-bit mode packet parity- check bit fcc pcb d0 d1 d21 d20 d19 d18 d17 serial data no pxl_crc rx/ sda tx/ scl uart/i 2 c forward control- channel bit d0 d1 d21 d0 d1 d15 d21 d20 d19 d18 d17 2 bits 16 video bits d16 d15 22 bits 22 video bits d16 6 pxl_crc bits pxl_crc on pxl_crc dbl = 0 d0 d1 d21 22 video bits* dbl = 1 d0 d1 d10 d11 d12 d21 11 x 2 video bits* d0 d1 d15 16 video bits* d0 d1 d7 d8 d9 d15 8 x 2 video bits* dbl = 0 dbl = 1 no pxl_crc, dbl = 0 58mhz max no pxl_crc, dbl = 1 116mhz max pxl_crc on, dbl = 0 58mhz max pxl_crc on, dbl = 1 116mhz max *internal bits. input/output pin availability may limit the external bus width. www.maximintegrated.com max96706 14-bit gmsl deserializer with coax or stp cable input
27-bit high-bandwidth mode ( figure 15 ) when bws = 0 and hibw = 1 (high-bandwidth mode) the 30-bit serial packet represents three 9b/10b symbols represent - ing 27 bits. after parity and control channel, this leaves 19/25 bits of video data if crc is/is not used (single mode), or 9/12 bits of video data if crc is/is not used (double mode). figure 15. 27-bit high-bandwidth mode serial-data format maxim integrated 28 27-bit mode packet parity- check bit fcc pcb d0 d1 d21 d20 d19 d18 d17 serial data no pxl_crc rx/ sda tx/ scl uart/i 2 c forward control- channel bit d0 d1 d24 d0 d1 d15 d24 d23 d22 d18 d17 2 bits 19 video bits d16 d15 25 bits 25 video bits d16 6 pxl_crc bits pxl_crc on pxl_crc dbl = 0 d0 d1 d24 25 video bits* dbl = 1 d0 d1 d11 d12 d13 d23 12 x 2 video bits* d0 d1 d18 19 video bits* d0 d1 d8 d9 d10 d17 9 x 2 video bits* dbl = 0 dbl = 1 no pxl_crc, dbl = 0 58mhz max no pxl_crc, dbl = 1 116mhz max pxl_crc on, dbl = 0 58mhz max pxl_crc on, dbl = 1 116mhz max d24 d23 d22 d18 d24 *internal bits. input/output pin availability may limit the external bus width. www.maximintegrated.com max96706 14-bit gmsl deserializer with coax or stp cable input
32-bit mode ( figure 16 ) when bws = 1 the 40-bit serial packet corresponds with four 8b/10b symbols, representing 32 bits (32-bit mode). after parity and control channel, this leaves 24/30 bits of video data if crc is/is not used (single mode), or 12/15 bits of video data if crc is/is not used (double mode). figure 16. 32-bit mode serial-data format maxim integrated 29 32-bit mode packet parity- check bit fcc pcb d0 d1 d24 d23 d29 d28 d27 serial data no pxl_crc rx/ sda tx/ scl uart/i 2 c forward control- channel bit d0 d2 d29 d0 d2 d23 d29 d28 d27 d26 d25 2 bits 24 video bits d26 d25 30 bits 30 video bits d24 6 pxl_crc bits pxl_crc on pxl_crc d0 d1 d29 30 video bits* d0 d1 d14 d15 d16 d29 15 x 2 video bits* d0 d1 d23 24 video bits* d0 d1 d11 d12 d13 d23 12 x 2 video bits* dbl = 0 dbl = 1 dbl = 0 dbl = 1 no pxl_crc, dbl = 0 43.5mhz max no pxl_crc, dbl = 1 87mhz max pxl_crc on, dbl = 0 43.5mhz max pxl_crc on, dbl = 1 87mhz max *internal bits. input/output pin availability may limit the external bus width. www.maximintegrated.com max96706 14-bit gmsl deserializer with coax or stp cable input
control channel and register programming the control channel sends i 2 c or uart information across the serial link for control of the serializer, deserial - izer, and any attached peripherals. the control channel is multiplexed onto the serial link and is available with or without the video channel. forward control channel control data sent from the serializer to the deserializer is sent on the forward control channel. the data is encoded as one of the serial bits in the forward high-speed link. after deserialization, the forward control-channel data is extracted from the serial link. the forward control-channel bandwidth exceeds the maximum external control data rate, and all data sent on the forward control channel appears on the remote side after transmission delay of a few bit times. reverse control channel control data sent from the deserializer to the serializer is sent on the reverse control channel. the data is encoded as a series of 1s pulses, with a maximum raw data rate of 1mbps. high-immunity mode is available to increase the robustness of the reverse control channel at a reduced raw bit rate of 500kbps ( table 1 ). setting the rev_fast bit = 1 increases this rate back to 1mbps. in i 2 c mode, when the input data rate (after encoding) exceeds the reverse data rate, the input clock is held through clock stretching to slow the external clock to match the internal bit rate. uart interface the uart interface, compatible with all gmsl devices, sends commands from device to device through several uart packets. set i2csel = 0 to set the device to use uart protocol. i 2 c interface the serial link connects the serializer and deserializer i 2 c interfaces together through the control channel. when an i 2 c master sends a command to one side of the link (local side) the control channel forwards this information to and from the other side of the link (remote side), allowing a single microcontroller to configure the serializer, deserializer, and peripherals. the microcontroller can be located on the serializer side (display applications) and the deserializer side (camera applications). dual-c opera - tions are supported as long as a software-arbitration method is used. the serial link assumes that only one microcontroller is talking at any given time. remote-end operation when an i 2 c master initiates communication on the local slave device (the serializer/deserializer directly connected to the master), the remote-side device acts as a master device that sends data forwarded from the local-side device, and forwards any data received from peripher - als attached to the remote-side device. this remote-side master device operates according to the timing settings in the i 2 c master setting register. set the master settings to match the timing settings used by the external microcon - troller. clock-stretch timing the i 2 c interface uses clock stretching to allow time for data to be forwarded across the serial link. the master microcontroller, along with any attached peripherals, must accept clock stretching of the gmsl devices. packet-based i 2 c a packet-based control channel is available for enhanced error handling of the control channel. this control-channel method handles simultaneous gpi/gpo and i 2 c trans - mission, along with error detection and retransmission. him pin setting revfast bit reverse control- channel mode max uart/i 2 c bit rate ( kbps ) low x legacy reverse control- channel mode (compatible with all gmsl devices) 1000 high 0 high-immunity mode 500 1 fast high-immunity mode (requires hibw = 0, serial-data rate > 1.25gbps) 1000 table 1. reverse control-channel modes x = dont care. maxim integrated 30 www.maximintegrated.com max96706 14-bit gmsl deserializer with coax or stp cable input
packet protocol summary the packet-based control channel uses a synchronous, symbol-based system to send data across the control channel. data to be sent across the control channel is split into symbols and stored in a transmit queue and then sent across the link. if both gpi and i 2 c data need to be sent (e.g., when gpi transitions during an i 2 c transmission) the symbols from both commands are combined in the queue. if the transmit queue is empty, idle packets are sent across the link to maintain control-channel lock. received i 2 c packets are output as determined by the microcontroller scl rate (local device), or the programmed master bit rate (remote device). the device holds scl low (clock stretch) until data has been received from the remote-side device. control-channel error detection and packet retransmission when the packet-based control channel is used, all pack - ets are checked for errors through crc. using 1, 5, or 8 bits, crc detects 1, 3, or 4 random bit errors in a packet. the transmitter retransmits packets whenever an error is detected. the transmitter sets a flag if a number of retries exceeds a programmed threshold. the receiver filters out packets with errors. gpo/gpi control gpo on the serializer follows gpi transitions on the deserializer. this gpo/gpi function can be used to transmit signals such as a frame sync in a surround-view camera system (see the providing a frame sync (camera applications) section). adaptive line equalizer the deserializer includes an adaptive line equalizer to compensate for higher cable attenuation at higher frequencies. the cable equalizer has 12 levels of com - pensation to handle up to 30m coax and 15m stp cable lengths. at initial lock, the adaptive equalizer selects the optimum compensation level. the device can be pro - grammed to re-adapt periodically, manually, or triggered from the eye-width monitor to compensate for any signifi - cant changes in the transmission environment. eye-width monitor the horizontal eye diagram opening is measured using the eye-width monitor. by default this measurement is done after link is established and also with 1 second intervals when link is running. eye width below a programmed threshold flags the errb output pin. a very low eye width restarts equalizer adaptation. spread-spectrum tracking the deserializer can track a spread input clock, eliminating the need for multiple spread clocks. cable-type confguration and input mux the driver inputs are programmable for two kinds of cable: 100 twisted pair and 50 coax (contact the factory for devices compatible with 75 cables). in coax mode, connect in0+ to out+ of the serializer. connect in1+ to out+ of the second serializer. control- channel data is sent to the serializer selected with the gmsl_in_sel bit. leave all unused in_ pins uncon - nected, or connect them to ground through 50 and a capacitor for increased power-supply rejection. if out- is not used, connect out- to v dd through a 50 resistor ( figure 17 ). when there are cs at the serializer, and at each deserializer, only one c can communicate at a time. disable forward and reverse channel links according to the communicating deserializer connection to prevent contention in i 2 c-to-i 2 c mode. figure 17. coax connection maxim integrated 31 out+ out- in+ optional components for increased power-supply rejection in- avdd 50? gm serializer gmsl deserializer www.maximintegrated.com max96706 14-bit gmsl deserializer with coax or stp cable input
crosspoint switch the crosspoint switch routes data between the parallel input/output and the serdes ( figure 18 ). the anything-to- anything routing assures the mapping between the video source and destination. shutdown/sleep modes several sleep and shutdown modes are available when full operation is not needed. confguration link when the high-speed video link is not needed, or unavail - able, a configuration link can be used in its place. in configuration-link mode, the parallel-digital input/output is disabled, the lock pin remains low, and the serial link internally generates its own clock, to allow full operation of the control channel (uart/i 2 c and gpio). serialization disable when the serial link is not needed, such as when down - stream devices are powered off, the user can disable serialization. in this mode, all forward communication is shut down. the user can reenable serialization either locally or through the reverse channel. sleep mode to reduce power consumption further, the devices can be put into sleep mode. in this mode, all registers keep their programmed values, and all functions in the device are powered down except for the wake-up detectors on the local i 2 c/uart interface, and the serial link. any activity seen by the wake-up detectors temporarily turns on the control-channel interface. during this time, a micro - controller can command the device to exit sleep mode. see the entering/exiting sleep mode section. power-down mode the lowest power-consumption mode is power-down mode. in this mode, all functions are powered down, and all register values are lost. link-startup procedure table 2 lists the startup procedure for image-sensing applications. the control channel is available after the video link or the configuration link is established. if the deserializer powers up after the serializer, the control channel becomes unavailable until 2ms after power-up. figure 18. crosspoint-switch dataflow maxim integrated 32 to output pins dout 0 : dout 1 dout 12 dout 13 : xbi 0 xbi 1 xbi 12 xbi 13 : : crossbar _ 4 dout _ 14 switches xbi 0 xbi 1 d 0 d 1 : : xbi 12 xbi 13 d 12 d 13 data 0 1 www.maximintegrated.com max96706 14-bit gmsl deserializer with coax or stp cable input
no. c serializer deserializer c connected to deserializer. set all confguration inputs. set all confguration inputs. 1 powers up. wait t pu . powers up and loads default settings. establishes video link when valid pclk available. powers up and loads default settings. locks to video-link signal if available. 1a (if no pclk) programs clinken, seren, and/or autoclink bits. wait 5ms after each command. establishes confguration link. locks to confg link if available. 1b (if not locked) sets any additional confguration bits that are mismatched between serializer and deserializer (e.g bws, cx/tp). wait 5ms for lock after each command. confguration changed. reestablishes confguration/ video link if needed. confguration changed. locks to confguration/video link. 2 sets register 0x07 confguration bits in the serializer (dbl, bws, hibw, edc, etc.). wait 2ms. confguration changed. reestablishes confg/video link if needed loss of lock may occur. 3 sets register 0x07 confguration bits in the deserializer (dbl, bws, hibw, edc, etc.). wait 5ms for lock to re-establish. confguration changed. locks to confguration/video link. 4 writes rest of serializer/deserializer confguration bits. confguration changed. confguration changed. 5 writes camera/peripheral confguration bits. forwards commands from c to serializer. forwards commands to camera/ peripherals. 5a if in confguration link: when pclk is available, set seren = 1. wait 5ms for lock. enables video link. locks to video link. table 2. link-startup procedure figure 19. state diagram maxim integrated 33 all states power - down or power off serial port locking config link operating program registers send gpi to gmsl serializer video link operating video link prbs test pwdnb = low or power off signal detected pwdnb = high, power on config link locked config link unlocked video link unlocked video link locked prbsen = 1 prbsen = 0 power on idle gpi changes from low to high or high to low sleep serial link activity stops or 8ms elapses after c sets sleep = 1 wake up signal sleep = 1, video link or config link not locked after 8ms 0 -- > sleep 0 --> sleep www.maximintegrated.com max96706 14-bit gmsl deserializer with coax or stp cable input
register map offset name msb lsb 0x00 seraddr[7:0] seraddr[6:0] rsvd 0x01 desaddr[7:0] desaddr[6:0] cfg - block 0x02 invpinh[7:0] invpinh[5:0] srng[1:0] 0x03 invpinl[7:0] invpinl[7:0] 0x04 main confg[7:0] locked outenb prbsen sleep inttype[1:0] revccen fwdccen 0x05 eqtune[7:0] i2c - method dcs hvtr_ mode en_eq eqtune[3:0] 0x06 hvsrc[7:0] rsvd max_rt_ en i2c_rt_ en gpi_ comp_en gpi_rt_ en hv_src[2:0] 0x07 confg[7:0] dbl drs bws es hibw hven cxtp pxl_crc 0x08 pktcc_en[7:0] lflt_en_ pos lflt_en_ neg gpi_en disstag err_rst pktcc_ en cc_crc_ length[1:0] 0x09 i2csrc a[7:0] i2c_src_a[6:0] rsvd 0x0a i2cdst a[7:0] i2c_dst_a[6:0] rsvd 0x0b i2csrc b[7:0] i2c_src_b[6:0] rsvd 0x0c i2cdst b[7:0] i2c_dst_b[6:0] rsvd 0x0d i2cconfg[7:0] i2c_loc_ ack i2c_slv_sh[1:0] i2c_mst_bt[2:0] i2c_slv_to[1:0] 0x0e det_thr[7:0] det_thr[7:0] 0x0f flt_track[7:0] gmsl_in_ sel en_de_ filt en_hs_ filt en_vs_ filt de_en htrack vtrack prbs_ type 0x10 rceg[7:0] rceg_type[1:0] rceg_ bound rceg_err_num[3:0] rceg_en 0x11 rceg2[7:0] rceg_err_rate[3:0] rceg_lo_bst_ prb[1:0] rceg_lo_bst_ len[1:0] 0x12 line_crc[7:0] under - bst_det_ en cc_crc_ err_en line_crc_loc[1:0] line_ crc_en dis_ rwake max_rt_ err_en rceg_ err_ per_en 0x13 ewm[7:0] ewm_en ewm_ per_ mode ewm_ man_ trg_req ewm_min_thr[4:0] 0x14 aeq[7:0] aeq_en aeq_ per_ mode aeq_ man_ trg_req ewm_per_thr[4:0] 0x15 det_err[7:0] det_err[7:0] 0x16 prbs_err[7:0] prbs_err[7:0] 0x17 lf[7:0] rsvd max_rt_ err prbs_ok gpi_in lf_neg[1:0] lf_pos[1:0] 0x18 rsvd_18[7:0] rsvd[7:0] 0x19 cc_crc_errcnt[7:0] cc_crc_errcnt[7:0] 0x1a rceg_err_cnt[7:0] rceg_err_cnt[7:0] maxim integrated 34 www.maximintegrated.com max96706 14-bit gmsl deserializer with coax or stp cable input
offset name msb lsb 0x1b i2csel[7:0] rsvd rsvd rsvd rsvd i2csel line_ crc_err rsvd rsvd 0x1c ewm_eye_width[7:0] rsvd rsvd eom_eye_width[5:0] 0x1d aeq_bst[7:0] rsvd rsvd rsvd under - boost_ det aeq_bst[3:0] 0x1e id[7:0] id[7:0] 0x1f revision[7:0] rsvd rsvd rsvd hdcpcap revision[3:0] 0x20 crcvalue 0[7:0] crcvalue_0_[7:0] 0x21 crcvalue 1[7:0] crcvalue_1_[7:0] 0x22 crcvalue 2[7:0] crcvalue_2_[7:0] 0x23 crcvalue 3[7:0] crcvalue_3_[7:0] 0x65 crossbar 0[7:0] crossbar_n_0[3:0] crossbar_n+1_0[3:0] 0x66 crossbar 2[7:0] crossbar_n_2[3:0] crossbar_n+1_2[3:0] 0x67 crossbar 4[7:0] crossbar_n_4[3:0] crossbar_n+1_4[3:0] 0x68 crossbar 6[7:0] crossbar_n_6[3:0] crossbar_n+1_6[3:0] 0x69 crossbar 8[7:0] crossbar_n_8[3:0] crossbar_n+1_8[3:0] 0x6a crossbar 10[7:0] crossbar_n_10[3:0] crossbar_n+1_10[3:0] 0x6b crossbar 12[7:0] crossbar_n_12[3:0] crossbar_n+1_12[3:0] 0x96 rsvd_96[7:0] rsvd[1:0] rsvd[1:0] rsvd rsvd rsvd rsvd 0x97 rev_fast[7:0] rev_fast rsvd rsvd[5:0] 0x98 rsvd_98[7:0] rsvd rsvd rsvd[5:0] 0x99 rsvd_99[7:0] rsvd rsvd rsvd rsvd rsvd rsvd rsvd rsvd 0x9a rsvd_9a[7:0] rsvd rsvd rsvd[1:0] rsvd[2:0] rsvd 0x9b rsvd_9b[7:0] rsvd rsvd[1:0] rsvd[2:0] rsvd[1:0] 0x9c rsvd_9c[7:0] rsvd rsvd[1:0] rsvd rsvd[3:0] 0x9d rsvd_9d[7:0] rsvd rsvd rsvd rsvd soft_ pd rsvd rsvd rsvd 0x9e rsvd_9e[7:0] rsvd rsvd[1:0] rsvd[2:0] rsvd rsvd 0x9f rsvd_9f[7:0] rsvd rsvd rsvd rsvd rsvd hpftune[1:0] rsvd 0xa0 rsvd_a0[7:0] rsvd rsvd rsvd[1:0] rsvd[3:0] 0xa1 rsvd_a1[7:0] rsvd[2:0] rsvd[4:0] 0xa2 rsvd_a2[7:0] rsvd[7:0] 0xa3 rsvd_a3[7:0] rsvd[3:0] rsvd[3:0] 0xa4 rsvd_a4[7:0] rsvd[2:0] rsvd rsvd rsvd rsvd[1:0] 0xa5 rsvd_a5[7:0] rsvd[3:0] rsvd[1:0] rsvd[1:0] 0xa6 rsvd_a6[7:0] rsvd rsvd rsvd rsvd rsvd[1:0] rsvd[1:0] maxim integrated 35 www.maximintegrated.com max96706 14-bit gmsl deserializer with coax or stp cable input
offset name msb lsb 0xc9 rsvd_c9[7:0] rsvd[7:0] 0xca rsvd_ca[7:0] rsvd rsvd rsvd rsvd[1:0] rsvd rsvd rsvd 0xcb cc_locked[7:0] rsvd rsvd rsvd rsvd cc_ wblock rem_ cclock cc_ wblock_ lost rsvd 0xcc rsvd_cc[7:0] rsvd rsvd[6:0] 0xcd rsvd_cd[7:0] rsvd rsvd[6:0] 0xfd rsvd_fd[7:0] rsvd[7:0] 0xfe rsvd_fe[7:0] rsvd[3:0] rsvd[3:0] 0xff rsvd_ff[7:0] rsvd rsvd rsvd rsvd rsvd[3:0] maxim integrated 36 www.maximintegrated.com max96706 14-bit gmsl deserializer with coax or stp cable input
seraddr (0x00) bit 7 6 5 4 3 2 1 0 field seraddr[6:0] rsvd reset 1000000b 0b access type write, read write, read bitfield bits description decode seraddr 7:1 serializer address: serializer device address 0000000: i 2 c write/read address is 0x00, 0x01 0000001: i 2 c write/read address is 0x02, 0x03 xxxxxxx: i 2 c write/read address is xxxxxxx0, xxxxxxx1 1111111: i 2 c write/read address is 0xfe, 0xff rsvd 0 reserved: do not change from default value 0: reserved desaddr (0x01) bit 7 6 5 4 3 2 1 0 field desaddr[6:0] cfgblock reset xxxxxxxb 0b access type write, read write, read bitfield bits description decode desaddr 7:1 deserializer address: deserializer device address (initial value depends on add3, add2, add1, and add0 pin settings latched at power-up) 0000000: i 2 c write/read address is 0x00, 0x01 0000001: i 2 c write/read address is 0x02, 0x03 xxxxxxx: i 2 c write/read address is xxxxxxx0, xxxxxxx1 1111111: i 2 c write/read address is 0xfe, 0xff cfgblock 0 confguration block. when 1, make all registers read only 0: set all write/read registers as writable 1: set all registers as read only invpinh (0x02) bit 7 6 5 4 3 2 1 0 field invpinh[5:0] srng[1:0] reset 000000b 11b access type write, read write, read bitfield bits description decode invpinh 7:2 invert output pins high: invert output pins d8Cd13 xxxxx0: do not invert d8 xxxxx1: invert d8 xxxx0x: do not invert d9 xxxx1x: invert d9 xxx0xx: invert d10 xxx1xx: do not invert d10 xx0xxx: do not invert d11 xx1xxx: invert d11 x0xxxx: do not invert d12 x1xxxx: invert d12 0xxxxx: do not invert d13 1xxxxx: invert d13 srng 1:0 serial data-rate range 00: 0.5 to 1gbps 01: 1 to 1.74gbps 1x: autodetect serial range maxim integrated 37 www.maximintegrated.com max96706 14-bit gmsl deserializer with coax or stp cable input
invpinl (0x03) bit 7 6 5 4 3 2 1 0 field invpinl[7:0] reset 00000000b access type write, read bitfield bits description decode invpinl 7:0 invert output pins low: invert output pins d0Cd7 xxxxxxx0: do not invert d0 xxxxxxx1: invert d0 xxxxxx0x: do not invert d1 xxxxxx1x: invert d1 xxxxx0xx: do not invert d2 xxxxx1xx: invert d2 xxxx0xxx: do not invert d3 xxxx1xxx: invert d3 xxx0xxxx: do not invert d4 xxx1xxxx: invert d4 xx0xxxxx: do not invert d5 xx1xxxxx: invert d5 x0xxxxxx: do not invert d6 x1xxxxxx: invert d6 0xxxxxxx: do not invert d7 1xxxxxxx: invert d7 main confg (0x04) bit 7 6 5 4 3 2 1 0 field locked outenb prbsen sleep inttype[1:0] revccen fwdccen reset xb 0b 0b 0b 01b 1b 1b access type read only write, read write, read write, read write, read write, read write, read bitfield bits description decode locked 7 lock output: lock output pin level 0: video link not locked 1: video link locked outenb 6 outputs enable bar: disable outputs 0: enable dout_outputs 1: disable dout_ outputs prbsen 5 prbs test enable 0: set device for normal operation 1: enable prbs test sleep 4 sleep mode: activate sleep mode 0: set device for normal operation 1: put device into sleep mode inttype 3:2 interface type: local control-channel interface when i2csel = 0 00: uart-to-i 2 c conversion 01: uart 1x: disable local control channel revccen 1 reverse control-channel enable : enable reverse control channel from deserializer 0: disable reverse control-channel receiver 1: enable reverser control-channel receiver fwdccen 0 forward control-channel enable: enable forward control channel to deserializer 0: disable forward control-channel transmitter 1: enable forward control-channel transmitter maxim integrated 38 www.maximintegrated.com max96706 14-bit gmsl deserializer with coax or stp cable input
eqtune (0x05) bit 7 6 5 4 3 2 1 0 field i2c - method dcs hvtr_ mode en_eq eqtune[3:0] reset 0b 0b 1b 1b 1001b access type write, read write, read write, read write, read write, read bitfield bits description decode i2cmethod 7 i 2 c method: skip register address when converting uart to i 2 c 0: send the register address during uart-to-i 2 c conversion 1: do not send the register address during uart-to-i 2 c conversion dcs 6 driver current selection: driver current selec - tion for cmos outputs 0: set device for normal operation 1: increase cmos driver current hvtr_mode 5 hv tracking mode: hv tracking allows continu - ous hsync format 0: use partial periodic hv tracking 1: use partial and full periodic hv tracking en_eq 4 enable equalizer: enable equalizer for manual and adaptive modes 0: disable equalization 1: enable equalization eqtune 3:0 equalizer tune: equalizer boost level at 750mhz (effective when adaptive eq is turned off) 0000: 1.6db manual eq setting 0001: 2.1db manual eq setting 0010: 2.8db manual eq setting 0011: 3.5db manual eq setting 0100: 4.3db manual eq setting 0101: 5.2db manual eq setting 0110: 6.3db manual eq setting 0111: 7.3db manual eq setting 1000: 8.5db manual eq setting 1001: 9.7db manual eq setting 1010: 11db manual eq setting 1011: 12.2db manual eq setting 11xx: do not use maxim integrated 39 www.maximintegrated.com max96706 14-bit gmsl deserializer with coax or stp cable input
hvsrc (0x06) bit 7 6 5 4 3 2 1 0 field rsvd max_rt_ en i2c_rt_en gpi_ comp_en gpi_rt_en hv_src[2:0] reset xb 1b 1b 0b 1b 111b access type write, read write, read write, read write, read write, read write, read bitfield bits description decode rsvd 7 reserved: do not change from de - fault value x: reserved max_rt_en 6 maximum retransmission limit enable 0: disable maximum retransmission limit 1: enable maximum retransmission limit i2c_rt_en 5 i 2 c retransmission enable 0: disable i 2 c retransmission 1: enable i 2 c retransmission gpi_comp_en 4 gpi compensation enable: gpi skew compensation enable 0: disable gpi skew compensation 1: enable gpi skew compensation gpi_rt_en 3 gpi retransmission enable 0: disable gpi retransmission 1: enable gpi retransmission hv_src 2:0 hs/vs source selection: hs/vs bit selection 000: use d18/d19 for hs/vs (use this setting when the serial - izer is a 3.125gbps device or if hibw mode is used; otherwise, this setting is for use with the max9273 when dbl = 0 or hven = 1) 001: use d14/d15 for hs/vs (for use with the max9271/ max96705 when dbl = 0 or hven = 1) 010: use d12/d13 for hs/vs (for use with the max96707 when dbl = 0 or hven = 1) 011: use d0/d1 for hs/vs (for use with the max9271/ max9273/max96705/max96707 when dbl = 1 and hven = 0) 10x: do not use 110: automatically determine the source of hsync/vsync (for use with the max96707) 111: automatically determine the source of hsync/vsync (for use with the max96705) maxim integrated 40 www.maximintegrated.com max96706 14-bit gmsl deserializer with coax or stp cable input
confg (0x07) bit 7 6 5 4 3 2 1 0 field dbl drs bws es hibw hven cxtp pxl_crc reset 0b 0b 0b 0b 0b 0b xb 0b access type write, read write, read write, read write, read write, read write, read write, read write, read bitfield bits description decode dbl 7 double-output mode 0: use single-rate output 1: use double-rate output (2x word rate at 1/2x width) drs 6 data-rate select 0: use normal data-rate output 1: use 1/2 rate data output (for use with low data rates) bws 5 bus-width select 0: set bus width for 22-/24-bit bus, 24-/27-bit mode (depending on hibw setting) 1: set bus width for 30-bit bus (32-bit mode) es 4 edge select 0: set output data valid on rising edge of pclkout 1: set output data valid on falling edge of pclkout hibw 3 high-bandwidth mode 0: disable high-bandwidth mode 1: enable high-bandwidth mode (when bws = 0) hven 2 hs/vs encoding enable 0: disable hs/vs encoding 1: enable hs/vs encoding cxtp 1 coax/tp select 0: use differential-output mode (for use with twisted-pair cable) 1: use single-ended output mode (for use with coax cable) pxl_crc 0 pixel crc enable: pixel error-detection type (this is controllable by pin when lccen = 0) 0: use 1-bit parity (compatible with all devices) 1: use 6-bit crc maxim integrated 41 www.maximintegrated.com max96706 14-bit gmsl deserializer with coax or stp cable input
pktcc_en (0x08) bit 7 6 5 4 3 2 1 0 field lflt_en_pos lflt_en_neg gpi_en disstag err_rst pktcc_en cc_crc_ length[1:0] reset 1b xb 1b 0b 0b 0b 01b access type write, read write, read write, read write, read write, read write, read write, read bitfield bits description decode lflt_en_pos 7 line-fault detector enable positive line: enable line-fault detector lmn0 0: disable line-fault detector lmn0 1: enable line-fault detector lmn0 lflt_en_neg 6 line-fault detector enable negative line: enable line-fault detector lmn1; disabled by default in coax mode and enabled by default in twisted-pair mode 0: disable line-fault detector lmn1 1: enable line-fault detector lmn1 gpi_en 5 gpi-to-gpo enable: enable gpi-to-gpo signal transmission to serializer 0: disable gpi-to-gpo transmission 1: enable gpi-to-gpo transmission disstag 4 disable staggering: disable staggering of outputs 0: enable staggering of dout_outputs 1: disable staggering of dout_outputs err_rst 3 error reset: when set to 1, automatically reset det_err and corr_err registers 1s after error pin is asserted 0: disable automatic reset of deterr_ and corr_err registers 1: enable automatic reset of deterr_ and corr_err registers pktcc_en 2 packet-based control-channel mode enable 0: disable packet-based control-channel mode 1: enable packet-based control-channel mode cc_crc_length 1:0 control-channel crc length 00: 1-bit crc 01: 5-bit crc 10: 8-bit crc 11: do not use i2csrc (0x09, 0x0b) bit 7 6 5 4 3 2 1 0 field i2c_src[6:0] rsvd reset 0b 0b access type write, read write, read bitfield bits description decode i2c_src 7:1 i 2 c address translator source: i 2 c address translator source a 0000000: i 2 c write/read address is 0x00, 0x01 0000001: i 2 c write/read address is 0x02, 0x03 xxxxxxx: i 2 c write/read address is xxxxxxx0, xxxxxxx1 1111111: i 2 c write/read address is 0xfe, 0xff rsvd 0 reserved: do not change from default value 0: reserved maxim integrated 42 www.maximintegrated.com max96706 14-bit gmsl deserializer with coax or stp cable input
i2cdst (0x0a, 0x0c) bit 7 6 5 4 3 2 1 0 field i2c_dst[6:0] rsvd reset 0b 0b access type write, read write, read bitfield bits description decode i2c_dst 7:1 i 2 c address translator destination: i 2 c address translator destination a 0000000: i 2 c write/read address is 0x00, 0x01 0000001: i 2 c write/read address is 0x02, 0x03 xxxxxxx: i 2 c write/read address is xxxxxxx0, xxxxxxx1 1111111: i 2 c write/read address is 0xfe, 0xff rsvd 0 reserved: do not change from default value 0: reserved i2cconfg (0x0d) bit 7 6 5 4 3 2 1 0 field i2c_loc_ack i2c_slv_sh[1:0] i2c_mst_bt[2:0] i2c_slv_to[1:0] reset 0b 01b 101b 10b access type write, read write, read write, read write, read bitfield bits description decode i2c_loc_ack 7 i 2 c-to-i 2 c slave local acknowledge: when forward channel is not available 0: disable local acknowledge when forward channel is not available 1: enable local acknowledge when forward channel is not available i2c_slv_sh 6:5 i 2 c-to-i 2 c slave setup and hold time setting: setup, hold (typ) 00: (352, 117)ns 01: (469, 234)ns 10: (938, 352)ns 11: (1406, 469)ns i2c_mst_bt 4:2 i 2 c-to-i 2 c master bit rate setting: min, typ, max. 000: (6.61, 8.47, 9.92)kbps bit rate 001: (22.1, 28.3, 33.2)kbps bit rate 010: (66.1, 84.7, 99.2)kbps bit rate 011: (82, 105, 123)kbps bit rate 100: (136, 173, 203)kbps bit rate 101: (265, 339, 397))kbps bit rate 110: (417, 533, 625)kbps bit rate 111: (654, 837, 980)kbps bit rate i2c_slv_to 1:0 i 2 c-to-i 2 c slave remote-side timeout setting: typ 00: 64s timeout 01: 256s timeout 10: 1024s timeout 11: i 2 c timeout disabled maxim integrated 43 www.maximintegrated.com max96706 14-bit gmsl deserializer with coax or stp cable input
det_thr (0x0e) bit 7 6 5 4 3 2 1 0 field det_thr[7:0] reset 00000000b access type write, read bitfield bits description decode det_thr 7:0 detected errors threshold: threshold for de - tected errors 00000000: value is 0 00000001: value is 1, xxxxxxxx 11111111: value is 255 flt_track (0x0f) bit 7 6 5 4 3 2 1 0 field gmsl_in_ sel en_de_ filt en_hs_ filt en_vs_ filt de_en htrack vtrack prbs_ type reset 0b 0b 0b 0b 0b 0b 0b 1b access type write, read write, read write, read write, read write, read write, read write, read write, read bitfield bits description decode gmsl_in_sel 7 select gmsl input 0: select in0+, in0- 1: select in1+, in1- en_de_filt 6 enable de glitch filtering: enable glitch fltering on dout11 0: disable glitch fltering on dout11 1: enable glitch fltering on dout11 en_hs_filt 5 enable hs glitch filtering: enable glitch fltering on dout12 0: disable glitch fltering on dout12 1: enable glitch fltering on dout12 en_vs_filt 4 enable vs glitch filtering: enable glitch fltering on dout13 0: disable glitch fltering on dout13 1: enable glitch fltering on dout13 de_en 3 de processing enable: enable processing sepa - rate hs and de signals 0: disable processing hs and de signals 1: enable processing hs and de signals htrack 2 hs tracking enable 0: disable hs tracking 1: enable hs tracking vtrack 1 vs tracking enable 0: disable vs tracking 1: enable vs tracking prbs_type 0 prbs type select: prbs type select (in hibw mode, set prbs_type = 0) 0: gmsl default style prbs test 1: max9272 style prbs maxim integrated 44 www.maximintegrated.com max96706 14-bit gmsl deserializer with coax or stp cable input
rceg (0x10) bit 7 6 5 4 3 2 1 0 field rceg_type[1:0] rceg_ bound rceg_err_num[3:0] rceg_en reset 00b 0b 0001b 0b access type write, read write, read write, read write, read bitfield bits description decode rceg_type 7:6 reverse-channel generated error type 00: random errors 01: short burst 1x: long burst rceg_bound 5 reverse-channel generated error bound - ary: effective when rceg_type_ = 0x) 0: errors are unbounded to symbols 1: errors are bounded to symbols rceg_err_num 4:1 number of rceg errors generated: num - ber of errors generated with each request effective when rceg_type_ = 0x) 0000: value is 0. 0001: value is 1 xxxx 1111: value is 15 rceg_en 0 enable reverse-channel error generator 0: disable reverse-channel error generator 1: enable reverse-channel error generator rceg2 (0x11) bit 7 6 5 4 3 2 1 0 field rceg_err_rate[3:0] rceg_lo_bst_prb[1:0] rceg_lo_bst_len[1:0] reset 1111b 00b 00b access type write, read write, read write, read bitfield bits description decode rceg_err_rate 7:4 error-generation rate: error-generation rate in terms of bit time = 2^(rceg_err_ rate+3). effective when rceg_type = 0x) 0000: rate is 2^-3 0001: rate is 2^-4 0010: rate is 2^-5 xxxx: rate is 2^-(3 + value) 1110: rate is 2^-17 1111: rate is 2^-18 rceg_lo_bst_prb 3:2 long-burst error probability: effective when rceg_type = 10) 00: 1/1024 01: 1/128 10: 1/32 11: 1/8 rceg_lo_bst_len 1:0 long-burst error length: long-burst error length in terms of bit time effective when rceg_type = 10) 00: continuous 01: 128 (~150us) 10: 8192 (~9.83ms) 11: 1048576 (~1.26s) maxim integrated 45 www.maximintegrated.com max96706 14-bit gmsl deserializer with coax or stp cable input
line_crc (0x12) bit 7 6 5 4 3 2 1 0 field under - bst_det_ en cc_crc_ err_en line_crc_loc[1:0] line_crc_ en dis_ rwake max_rt_ err_en rceg_ err_per_ en reset 0b 1b 01b 0b 0b 1b 0b access type write, read write, read write, read write, read write, read write, read write, read bitfield bits description decode underbst_det_en 7 underboost-detection enable: allow under - boost detection driving errorb pin 0: disable underboost detection driving error pin 1: enable underboost detection driving error pin cc_crc_err_en 6 control-channel crc err enable: enable reporting of (cc_crc_err_cnt -> 0) on the errb pin 0: disable reporting of errors on errb 1: enable reporting of errors on errb line_crc_loc 5:4 video-line crc insertion location 00: [1..4] 01: [5..8] 10: [9..12] 11: [13..16] line_crc_en 3 video-line crc enable 0: disable video-line crc 1: enable video-line crc dis_rwake 2 disable remote wake-up 0: enable remote wake-up 1: disable remote wake-up max_rt_err_en 1 enable refection of maximum retransmis - sion error: enable refection of maximum retransmission error on the errorb pin 0: disable maximum retransmission error on the error pin 1: enable maximum retransmission error on the error pin rceg_err_per_en 0 periodic error-generation enable: effective when rceg_type = 0x) 0: disable periodic-error generator 1: enable periodic-error generator maxim integrated 46 www.maximintegrated.com max96706 14-bit gmsl deserializer with coax or stp cable input
ewm (0x13) bit 7 6 5 4 3 2 1 0 field ewm_en ewm_per_ mode ewm_ man_trg_ req ewm_min_thr[4:0] reset 1b 1b 0b 01101b access type write, read write, read write 1 to set, read write, read bitfield bits description decode ewm_en 7 eye-width monitor enable 0: disable eye-width monitor 1: enable eye-width monitor ewm_per_mode 6 eye-width monitor periodic mode select 0: set eye-width monitor to use nonperi - odic mode 1: set eye-width monitor to use periodic mode ewm_man_trg_req 5 eye-width manual trigger request: rising edge of this register triggers eye-width monitor when not in periodic mode 0: do not trigger eye-width monitor. 1: write 1 to this bit to manually trigger the eye-width monitor ewm_min_thr 4:0 eye-width minimum threshold: eye-width minimum threshold for fagging errorb pin 00000: eye-width threshold is disabled xxxxx: (ewm_min_thr/64)% open eye fags error pin aeq (0x14) bit 7 6 5 4 3 2 1 0 field aeq_en aeq_per_ mode aeq_man_ trg_req ewm_per_thr[4:0] reset 1b 0b 0b 00000b access type write, read write, read write 1 to set, read write, read bitfield bits description decode aeq_en 7 adaptive equalization enable: enable adap - tive equalization 0: disable aeq 1: enable aeq aeq_per_mode 6 adaptive equalization periodic mode select 0: set aeq to use nonperiodic mode 1: set aeq to use periodic mode aeq_man_trg_req 5 adaptive equalization manual fine-tune request: rising edge of this register triggers aeq fne tuning when not in periodic mode 0: do not trigger aeq fne tuning 1: write 1 to this bit to manually trigger the aeq fne tuning ewm_per_thr 4:0 eye-width trigger threshold: eye-width threshold to trigger a fne tune operation 00000: eye-opening threshold is disabled 10000: 50% open-eye triggers fne-tune operation other: do not use maxim integrated 47 www.maximintegrated.com max96706 14-bit gmsl deserializer with coax or stp cable input
det_err (0x15) bit 7 6 5 4 3 2 1 0 field det_err[7:0] reset xxxxxxxxb access type read only bitfield bits description decode det_err 7:0 detected error counter 00000000: value is 0 00000001: value is 1 xxxxxxxx 11111111: value is 255. prbs_err (0x16) bit 7 6 5 4 3 2 1 0 field prbs_err[7:0] reset xxxxxxxxb access type read only bitfield bits description decode prbs_err 7:0 prbs error counter 00000000: value is 0 00000001: value is 1 xxxxxxxx 11111111: value is 255 lf (0x17) bit 7 6 5 4 3 2 1 0 field rsvd max_rt_ err prbs_ok gpi_in lf_neg[1:0] lf_pos[1:0] reset xb xb xb xb xxb xxb access type read only read clears all read only read only read only read only bitfield bits description decode rsvd 7 reserved: do not change from default value x: reserved max_rt_err 6 maximum retransmission error bit: goes high if packet control channel hits maximum retransmission limit; cleared when read 0: no control-channel retransmission error 1: control-channel retransmission maximum limit reached prbs_ok 5 prbs ok: max9271/max9273-compatible prbs test for link is terminated normally; check prbs_err register for the prbs success; for other serdes read prbs_err registers 0: no max9271/max9273-compatible prbs test completed 1: max9271/max9273-compatible prbs test completed normally gpi_in 4 gpi pin level 0: gpi is input low 1: gpi is input high lf_neg 3:2 line fault: line-fault status of the indicated input lf_pos -> lmn0 lf_neg -> lmn1 00: short to battery detected 01: short to ground detected 10: no faults detected 11: open cable detected lf_pos 1:0 line fault: line-fault status of the indicated input lf_pos -> lmn0 lf_neg -> lmn1 00: short to battery detected 01: short to ground detected 10: no faults detected 11: open cable detected maxim integrated 48 www.maximintegrated.com max96706 14-bit gmsl deserializer with coax or stp cable input
rsvd_18 (0x18) bit 7 6 5 4 3 2 1 0 field rsvd[7:0] reset xxxxxxxxb access type read only bitfield bits description decode rsvd 7:0 reserved: do not change from default value xxxxxxxx: reserved cc_crc_errcnt (0x19) bit 7 6 5 4 3 2 1 0 field cc_crc_errcnt[7:0] reset xxxxxxxxb access type read only bitfield bits description decode cc_crc_errcnt 7:0 packet-based control-channel crc error counter 00000000: value is 0 00000001: value is 1 xxxxxxxx 11111111: value is 255 rceg_err_cnt (0x1a) bit 7 6 5 4 3 2 1 0 field rceg_err_cnt[7:0] reset xxxxxxxxb access type read only bitfield bits description decode rceg_err_cnt 7:0 control-channel number of generated errors 00000000: value is 0 00000001: value is 1. xxxxxxxx 11111111: value is 255 maxim integrated 49 www.maximintegrated.com max96706 14-bit gmsl deserializer with coax or stp cable input
i2csel (0x1b) bit 7 6 5 4 3 2 1 0 field rsvd rsvd rsvd rsvd i2csel line_crc_ err rsvd rsvd reset 0b 0b 0b 0b xb xb xb xb access type write, read write, read write, read write, read read only read clears all read only read only bitfield bits description decode rsvd 7 reserved: do not change from default value 0: reserved rsvd 6 reserved: do not change from default value 0: reserved rsvd 5 reserved: do not change from default value 0: reserved rsvd 4 reserved: do not change from default value 0: reserved i2csel 3 i2csel pin level: detected i2csel pin level 0: low-i2csel pin detected (uart) 1: high-i2csel pin detected (i2c) line_crc_ err 2 crc-error bit: goes high if received video line has crc mismatch and latched; cleared to 0 when read 0: no line crc error detected 1: line crc error detected rsvd 1 reserved: do not change from default value x: reserved rsvd 0 reserved: do not change from default value x: reserved ewm_eye_width (0x1c) bit 7 6 5 4 3 2 1 0 field rsvd rsvd eom_eye_width[5:0] reset 0b 0b xxxxxxb access type write, read write, read read only bitfield bits description decode rsvd 7 reserved: do not change from default value 0: reserved rsvd 6 reserved: do not change from default value 0: reserved eom_eye_width 5:0 measured eye opening: opening width = eom_eye_width / 63 * 100% 000000: width is 0% 000001: width is 1/63 x 100% 111111: width is 63/63 x 100% maxim integrated 50 www.maximintegrated.com max96706 14-bit gmsl deserializer with coax or stp cable input
aeq_bst (0x1d) bit 7 6 5 4 3 2 1 0 field rsvd rsvd rsvd under - boost_ det aeq_bst[3:0] reset 0b 0b 0b xb xxxxb access type write, read write, read write, read read only read only bitfield bits description decode rsvd 7 reserved: do not change from default value 0: reserved rsvd 6 reserved: do not change from default value 0: reserved rsvd 5 reserved: do not change from default value 0: reserved underboost_det 4 underboost detected: '1' indicates that an underboost is detected when the aeq is at the maximum setting 0: normal operation 1: underboost (at maximum aeq gain) detected aeq_bst 3:0 adaptive equalizer boost value: selected adaptive equalizer value; settings correspond to gain at 750mhz 0000: 1.6db eq setting 0001: 2.1db eq setting 0010: 2.8db eq setting 0011: 3.5db eq setting 0100: 4.3db eq setting 0101: 5.2db eq setting 0110: 6.3db eq setting 0111: 7.3db eq setting 1000: 8.5db eq setting 1001: 9.7db eq setting 1010: 11db eq setting 1011: 12.2db eq setting 11xx: reserved id (0x1e) bit 7 6 5 4 3 2 1 0 field id[7:0] reset xxxxxxxxb access type read only bitfield bits description decode id 7:0 device id: 8-bit value depends on the gmsl device attached 01001010: max96706 01001100: max96708 maxim integrated 51 www.maximintegrated.com max96706 14-bit gmsl deserializer with coax or stp cable input
revision (0x1f) bit 7 6 5 4 3 2 1 0 field rsvd rsvd rsvd hdcpcap revision[3:0] reset 0b 0b 0b xb xxxxb access type write, read write, read write, read read only read only bitfield bits description decode rsvd 7 reserved: do not change from default value 0: reserved rsvd 6 reserved: do not change from default value 0: reserved rsvd 5 reserved: do not change from default value 0: reserved hdcpcap 4 hdcp capability: '1' = hdcp capable 0: device does not have hdcp 1: device is hdcp capable revision 3:0 device revision 0000: value is 0 0001: value is 1 1111: value is 15 crcvalue (0x20 to 0x23) bit 7 6 5 4 3 2 1 0 field crcvalue[7:0] reset xxxxxxxxb access type read only bitfield bits description decode crcvalue 7:0 crc value: crc output for latest line; crc_value_3 to crc_value_0 represents crc[31:0]. 00000000: value is 0 00000001: value is 1 11111111: value is 255 crossbar (0x65 to 0x6b) bit 7 6 5 4 3 2 1 0 field crossbar_n[3:0] crossbar_n+1[3:0] reset xxxxb xxxxb access type write, read write, read bitfield bits description decode crossbar_n 7:4 crossbar setting: crossbar selects the internal signal to connect to the output pin, dout_. register crossbar_(n) contains settings for two outputs, with crossbar_(n) at d[7:4] and crossbar_(n+1) at d[3:0]. default settings for crossbar(n) connects internal signal d(n) to its respective dout(n) pin. 0000: connect d0 to output 0001: connect d1 to output :: : 1101: connect d13 to output 1110: force output low 1111: force output high crossbar_n+1 3:0 crossbar setting: crossbar selects the internal signal to connect to the output pin, dout_. register crossbar_(n) contains settings for two outputs, with crossbar_(n) at d[7:4] and crossbar_(n+1) at d[3:0]. default settings for crossbar(n) connects internal signal d(n) to its respective dout(n) pin. 0000: connect d0 to output 0001: connect d1 to output :: : 1101: connect d13 to output 1110: force output low 1111: force output high maxim integrated 52 www.maximintegrated.com max96706 14-bit gmsl deserializer with coax or stp cable input
rsvd_96 (0x96) bit 7 6 5 4 3 2 1 0 field rsvd[1:0] rsvd[1:0] rsvd rsvd rsvd rsvd reset 01b 01b 0b 0b 0b 1b access type write, read write, read write, read write, read write, read write, read bitfield bits description decode rsvd 7:6 reserved: do not change from default value 01: reserved rsvd 5:4 reserved: do not change from default value 01: reserved rsvd 3 reserved: do not change from default value 0: reserved rsvd 2 reserved: do not change from default value 0: reserved rsvd 1 reserved: do not change from default value 0: reserved rsvd 0 reserved: do not change from default value 1: reserved rev_fast (0x97) bit 7 6 5 4 3 2 1 0 field rev_fast rsvd rsvd[5:0] reset 0b 0b 100010b access type write, read write, read write, read bitfield bits description decode rev_ fast 7 reverse-channel fast mode 0: disable reverse-channel fast mode 1: enable reverse-channel fast mode rsvd 6 reserved: do not change from default value 0: reserved rsvd 5:0 reserved: do not change from default value 100010: reserved rsvd_98 (0x98) bit 7 6 5 4 3 2 1 0 field rsvd rsvd rsvd[5:0] reset 1b 0b 011010b access type write, read write, read write, read bitfield bits description decode rsvd 7 reserved: do not change from default value 1: reserved rsvd 6 reserved: do not change from default value 0: reserved rsvd 5:0 reserved: do not change from default value 011010: reserved maxim integrated 53 www.maximintegrated.com max96706 14-bit gmsl deserializer with coax or stp cable input
rsvd_99 (0x99) bit 7 6 5 4 3 2 1 0 field rsvd rsvd rsvd rsvd rsvd rsvd rsvd rsvd reset 0b 1b 0b 0b 0b 0b 0b 0b access type write, read write, read write, read write, read write, read write, read write, read write, read bitfield bits description decode rsvd 7 reserved: do not change from default value 0: reserved rsvd 6 reserved: do not change from default value 1: reserved rsvd 5 reserved: do not change from default value 0: reserved rsvd 4 reserved: do not change from default value 0: reserved rsvd 3 reserved: do not change from default value 0: reserved rsvd 2 reserved: do not change from default value 0: reserved rsvd 1 reserved: do not change from default value 0: reserved rsvd 0 reserved: do not change from default value 0: reserved rsvd_9a (0x9a) bit 7 6 5 4 3 2 1 0 field rsvd rsvd rsvd[1:0] rsvd[2:0] rsvd reset 0b 0b 10b 010b 0b access type write, read write, read write, read write, read write, read bitfield bits description decode rsvd 7 reserved: do not change from default value 0: reserved rsvd 6 reserved: do not change from default value 0: reserved rsvd 5:4 reserved: do not change from default value 10: reserved rsvd 3:1 reserved: do not change from default value 010: reserved rsvd 0 reserved: do not change from default value 0: reserved maxim integrated 54 www.maximintegrated.com max96706 14-bit gmsl deserializer with coax or stp cable input
rsvd_9b (0x9b) bit 7 6 5 4 3 2 1 0 field rsvd rsvd[1:0] rsvd[2:0] rsvd[1:0] reset 0b 01b 001b 10b access type write, read write, read write, read write, read bitfield bits description decode rsvd 7 reserved: do not change from default value 0: reserved rsvd 6:5 reserved: do not change from default value 01: reserved rsvd 4:2 reserved: do not change from default value 001: reserved rsvd 1:0 reserved: do not change from default value 10: reserved rsvd_9c (0x9c) bit 7 6 5 4 3 2 1 0 field rsvd rsvd[1:0] rsvd rsvd[3:0] reset 0b 10b 1b 0100b access type write, read write, read write, read write, read bitfield bits description decode rsvd 7 reserved: do not change from default value 0: reserved rsvd 6:5 reserved: do not change from default value 10: reserved rsvd 4 reserved: do not change from default value 1: reserved rsvd 3:0 reserved: do not change from default value 0100: reserved rsvd_9d (0x9d) bit 7 6 5 4 3 2 1 0 field rsvd rsvd rsvd rsvd soft_pd rsvd rsvd rsvd reset 0b 0b 1b 01b 0b 0b 0b 0b access type write, read write, read write, read write, read write 1 to set, read write, read write, read write, read bitfield bits description decode rsvd 7 reserved: do not change from default value 0: reserved rsvd 6 reserved: do not change from default value 0: reserved rsvd 5 reserved: do not change from default value 1: reserved rsvd 4 reserved: do not change from default value 01: reserved soft_pd 3 reserved: do not change from default value 0: normal operation 1: reset the device rsvd 2 reserved: do not change from default value 0: reserved rsvd 1 reserved: do not change from default value 0: reserved rsvd 0 reserved: do not change from default value 0: reserved maxim integrated 55 www.maximintegrated.com max96706 14-bit gmsl deserializer with coax or stp cable input
rsvd_9e (0x9e) bit 7 6 5 4 3 2 1 0 field rsvd rsvd[1:0] rsvd[2:0] rsvd rsvd reset 1b 10b 010b 0b 0b access type write, read write, read write, read write, read write, read bitfield bits description decode rsvd 7 reserved: do not change from default value 1: reserved rsvd 6:5 reserved: do not change from default value 10: reserved rsvd 4:2 reserved: do not change from default value 010: reserved rsvd 1 reserved: do not change from default value 0: reserved rsvd 0 reserved: do not change from default value 0: reserved rsvd_9f (0x9f) bit 7 6 5 4 3 2 1 0 field rsvd rsvd rsvd rsvd rsvd hpftune[1:0] rsvd reset 0b 0b 0b 0b 0b 01b 0b access type write, read write, read write, read write, read write, read write, read write, read bitfield bits description decode rsvd 7 reserved: do not change from default value 0: reserved rsvd 6 reserved: do not change from default value 0: reserved rsvd 5 reserved: do not change from default value 0: reserved rsvd 4 reserved: do not change from default value 0: reserved rsvd 3 reserved: do not change from default value 0: reserved hpftune 2:1 equalizer high-pass filter cutoff frequency 00: 7.5mhz cutoff frequency 01: 3.75mhz cutoff frequency 10: 2.5mhz cutoff frequency 11: 1.87mhz cutoff frequency rsvd 0 reserved: do not change from default value 0: reserved rsvd_a0 (0xa0) bit 7 6 5 4 3 2 1 0 field rsvd rsvd rsvd[1:0] rsvd[3:0] reset 1b 0b 10b 1110b access type write, read write, read write, read write, read bitfield bits description decode rsvd 7 reserved: do not change from default value 1: reserved rsvd 6 reserved: do not change from default value 0: reserved rsvd 5:4 reserved: do not change from default value 10: reserved rsvd 3:0 reserved: do not change from default value 1110: reserved maxim integrated 56 www.maximintegrated.com max96706 14-bit gmsl deserializer with coax or stp cable input
rsvd_a1(0xa1) bit 7 6 5 4 3 2 1 0 field rsvd[2:0] rsvd[4:0] reset 010b 00100b access type write, read write, read bitfield bits description decode rsvd 7:5 reserved: do not change from default value 010: reserved rsvd 4:0 reserved: do not change from default value 00100: reserved rsvd_a2 (0xa2) bit 7 6 5 4 3 2 1 0 field rsvd[7:0] reset 00100000b access type write, read bitfield bits description decode rsvd 7:0 reserved: do not change from default value 00100000: reserved rsvd_a3 (0xa3) bit 7 6 5 4 3 2 1 0 field rsvd[3:0] rsvd[3:0] reset 0110b 1011b access type write, read write, read bitfield bits description decode rsvd 7:4 reserved: do not change from default value 0110: reserved rsvd 3:0 reserved: do not change from default value 1011: reserved rsvd_a4 (0xa4) bit 7 6 5 4 3 2 1 0 field rsvd[2:0] rsvd rsvd rsvd rsvd[1:0] reset 101b 1b 0b 1b 01b access type write, read write, read write, read write, read write, read bitfield bits description decode rsvd 7:5 reserved: do not change from default value 101: reserved rsvd 4 reserved: do not change from default value 1: reserved rsvd 3 reserved: do not change from default value 0: reserved rsvd 2 reserved: do not change from default value 1: reserved rsvd 1:0 reserved: do not change from default value 01: reserved maxim integrated 57 www.maximintegrated.com max96706 14-bit gmsl deserializer with coax or stp cable input
rsvd_a5 (0xa5) bit 7 6 5 4 3 2 1 0 field rsvd[3:0] rsvd[1:0] rsvd[1:0] reset 1100b 11b 01b access type write, read write, read write, read bitfield bits description decode rsvd 7:4 reserved: do not change from default value 1100: reserved rsvd 3:2 reserved: do not change from default value 11: reserved rsvd 1:0 reserved: do not change from default value 01: reserved rsvd_a6 (0xa6) bit 7 6 5 4 3 2 1 0 field rsvd rsvd rsvd rsvd rsvd[1:0] rsvd[1:0] reset 0b 0b 0b 0b 00b 01b access type write, read write, read write, read write, read write, read write, read bitfield bits description decode rsvd 7 reserved: do not change from default value 0: reserved rsvd 6 reserved: do not change from default value 0: reserved rsvd 5 reserved: do not change from default value 0: reserved rsvd 4 reserved: do not change from default value 0: reserved rsvd 3:2 reserved: do not change from default value 00: reserved rsvd 1:0 reserved: do not change from default value 01: reserved rsvd_c9 (0xc9) bit 7 6 5 4 3 2 1 0 field rsvd[7:0] reset xxxxxxxxb access type read only bitfield bits description decode rsvd 7:0 reserved: do not change from default value xxxxxxxx: reserved maxim integrated 58 www.maximintegrated.com max96706 14-bit gmsl deserializer with coax or stp cable input
rsvd_ca (0xca) bit 7 6 5 4 3 2 1 0 field rsvd rsvd rsvd rsvd[1:0] rsvd rsvd rsvd reset 0b xb xb xxb xb xb xb access type write, read read only read only read only read only read only read only bitfield bits description decode rsvd 7 reserved: do not change from default value 0: reserved rsvd 6 reserved: do not change from default value x: reserved rsvd 5 reserved: do not change from default value x: reserved rsvd 4:3 reserved: do not change from default value xx: reserved rsvd 2 reserved: do not change from default value x: reserved rsvd 1 reserved: do not change from default value x: reserved rsvd 0 reserved: do not change from default value x: reserved cc_locked (0xcb) bit 7 6 5 4 3 2 1 0 field rsvd rsvd rsvd rsvd cc_ wblock rem_ cclock cc_ wblock_ lost rsvd reset xb xb xb xb xb xb xb 0b access type read only read only read only read only read only read only read only write, read bitfield bits description decode rsvd 7 reserved: do not change from default value x: reserved rsvd 6 reserved: do not change from default value x: reserved rsvd 5 reserved: do not change from default value x: reserved rsvd 4 reserved: do not change from default value x: reserved cc_ wblock 3 control-channel word boundary locked: '1' indicates locked. 0: control-channel word boundary not locked. 1: control-channel word boundary locked. rem_ cclock 2 remote-side cc locked: '1' indicates remote side cc locked. 0: remote-side control channel not locked. 1: remote-side control channel locked. cc_ wblock_ lost 1 word-boundary lock lost: this bit is set to 1 when reverse control-channel word boundary loses lock. it is cleared when read. 0: normal operation 1: control-channel word boundary lost lock. rsvd 0 reserved: do not change from default value 0: reserved maxim integrated 59 www.maximintegrated.com max96706 14-bit gmsl deserializer with coax or stp cable input
rsvd_cc (0xcc) bit 7 6 5 4 3 2 1 0 field rsvd rsvd[6:0] reset 0b xxxxxxxb access type write, read read only bitfield bits description decode rsvd 7 reserved: do not change from default value 0: reserved rsvd 6:0 reserved: do not change from default value xxxxxxx: reserved rsvd_cd (0xcd) bit 7 6 5 4 3 2 1 0 field rsvd rsvd[6:0] reset 0b xxxxxxxb access type write, read read only bitfield bits description decode rsvd 7 reserved: do not change from default value 0: reserved rsvd 6:0 reserved: do not change from default value xxxxxxx: reserved rsvd_fd (0xfd) bit 7 6 5 4 3 2 1 0 field rsvd[7:0] reset 0b access type write, read bitfield bits description decode rsvd 7:0 reserved: do not change from default value 0: reserved rsvd_fe (0xfe) bit 7 6 5 4 3 2 1 0 field rsvd[3:0] rsvd[3:0] reset 0b 0b access type write, read write, read bitfield bits description decode rsvd 7:4 reserved: do not change from default value 0: reserved rsvd 3:0 reserved: do not change from default value 0: reserved maxim integrated 60 www.maximintegrated.com max96706 14-bit gmsl deserializer with coax or stp cable input
rsvd_ff (0xff) bit 7 6 5 4 3 2 1 0 field rsvd rsvd rsvd rsvd rsvd[3:0] reset 0b 0b 0b 0b xxxxb access type write, read write, read write, read write, read read only bitfield bits description decode rsvd 7 reserved: do not change from default value 0: reserved rsvd 6 reserved: do not change from default value 0: reserved rsvd 5 reserved: do not change from default value 0: reserved rsvd 4 reserved: do not change from default value 0: reserved rsvd 3:0 reserved: do not change from default value xxxx: reserved maxim integrated 61 www.maximintegrated.com max96706 14-bit gmsl deserializer with coax or stp cable input
applications information parallel interface the cmos parallel-interface data width is programmable and depends on the application. using a larger width (bws = 1) results in a lower-pixel clock rate, while a smaller width (bws = 0) allows a higher-pixel clock rate. bus data width the bus data width depends on the selected modes. the available bus width is less when using error detection or when in double mode (dbl = 1). table 3 shows the avail - able bit widths and default mapping for various modes. bus data rates the bus data rate depends on the settings bws and dbl. table 4 lists the available pclk rates available for different bus-width settings. for lower pclk rates, set dbl = 0 (if dbl = 1 in both the serializer and deserializer). crossbar switch by default, the crossbar switch connects the serializer input pins din_ and hs/vs (when hv encoding is used) to the corresponding deserializer output pins dout_ and hs/vs when dbl of the serializer and deserializer match. when there is a dbl mismatch use tables 5 - 7 to map the serial bits to the crossbar inputs. reprogram the crossbar switch when changing the output pin assignments. crossbar switch programming each output pin can be assigned any of the 14 dout signals. multiple outputs can share the same input. to force an output low, and ignore the input, set crossbar_ bit = 1110. to force an output high set crossbar_ = 1111. recommended crossbar switch programming procedure the following procedure programs the crossbar switch to reassign input/output pin locations: 1) for the crossbar output equivalent of dout0 (xbo0) select which pin to map (e.g., dout4 -> xbi4). 2) set the crossbar bits (crossbar0) to the desired selected mapped input (e.g., crossbar0 = 0100). 3) repeat for the other crossbar outputs. register bit settings output mapping dbl bws hibw pxl_ crc hven 1 1 1 1 dout11:0, hs, vs 1 1 1 0 dout11:0 1 1 0 1 dout11:0*, hs, vs 1 1 0 0 dout13:0* 1 0 1 1 dout8:0, hs, vs 1 0 1 0 dout11:0, hs, vs 1 0 0 1 1 dout7:0, hs, vs 1 0 0 1 0 dout7:0 1 0 0 0 1 dout10:0, hs, vs 1 0 0 0 0 dout10:0 0 1 1 1 dout11:0*, hs, vs 0 1 1 0 dout13:0* 0 1 0 1 dout11:0*, hs, vs 0 1 0 0 dout13:0* 0 0 1 dout11:0*, hs, vs 0 0 0 1 1 dout11:0*, hs, vs 0 0 0 1 0 dout13:0* 0 0 0 0 1 dout11:0*, hs, vs 0 0 0 0 0 dout13:0* table 3. output-data width selection * the bit width is limited by the number of available outputs. table 4. data-rate selection table * use drs = 1 with legacy devices only (max92xx). drs dbl bws hibw pclk range (mhz) 0 1 1 0 25 to 87 0 1 0 0 33.3 to 116 0 1 0 1 73.3 to 116 0 0 1 0 12.5 to 43.5 0 0 0 0 16.7 to 58 0 0 0 1 36.7 to 58 1* 0 1 0 6.25 to 12.5 1* 0 0 0 8.33 to 16.7 maxim integrated 62 www.maximintegrated.com max96706 14-bit gmsl deserializer with coax or stp cable input
table 5. output map (dbl = 0 or dbl = 1, first word) bit setting output bits (first word) db hv bw hb cr de sc* a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 0 0 x 0 x 0 1 0 1 2 3 4 5 6 7 8 9 10 11 14 15 0 0 x 0 x 1 1 0 1 2 3 4 5 6 7 8 9 10 13 14 15 0 0 x 0 x x 2 0 1 2 3 4 5 6 7 8 9 10 11 12 13 0 1 x 0 x 1 1 0 1 2 3 4 5 6 7 8 9 10 13 h v 0 1 x 0 x 1 2 0 1 2 3 4 5 6 7 8 9 10 11 h v 0 1 x 0 x 0 1,2 0 1 2 3 4 5 6 7 8 9 10 11 h v 0 0 0 1 x 0 0 0 1 2 3 4 5 6 7 8 9 10 11 h v 0 0 0 1 x 1 0 0 1 2 3 4 5 6 7 8 9 10 d h v 1 0 0 0 0 x 3 0 1 2 3 4 5 6 7 8 9 10 z z z 1 0 0 0 1 x 3 0 1 2 3 4 5 6 7 z z z z z z 1 0 1 0 0 x 3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 1 0 1 0 1 x 3 0 1 2 3 4 5 6 7 8 9 10 11 z z 1 1 0 0 0 0 1,2 0 1 2 3 4 5 6 7 8 9 10 z hl vl 1 1 0 0 0 1 1,2 0 1 2 3 4 5 6 7 8 9 z 10 hl vl 1 1 0 0 1 0 1,2 0 1 2 3 4 5 6 7 z z z z hl vl 1 1 0 0 1 1 1,2 0 1 2 3 4 5 6 z z z z 7 hl vl 1 1 1 0 0 1 1 0 1 2 3 4 5 6 7 8 9 10 13 hl vl 1 1 1 0 0 1 2 0 1 2 3 4 5 6 7 8 9 10 11 hl vl 1 1 1 0 0 0 1,2 0 1 2 3 4 5 6 7 8 9 10 11 hl vl 1 1 1 0 1 x 1,2 0 1 2 3 4 5 6 7 8 9 10 11 hl vl 1 0 0 1 0 0 0 0 1 2 3 4 5 6 7 8 9 10 11 hl vl 1 0 0 1 0 1 0 0 1 2 3 4 5 6 7 8 9 10 dl hl vl 1 0 0 1 1 0 0 0 1 2 3 4 5 6 7 8 z z z hl vl 1 0 0 1 1 1 0 0 1 2 3 4 5 6 7 8 z z dl hl vl maxim integrated 63 www.maximintegrated.com max96706 14-bit gmsl deserializer with coax or stp cable input
table 6. output map (dbl = 1, second word) table 7. legend bit setting output bits (second word) db hv bw hb cr de sc* b0 b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 b12 b13 1 0 0 0 0 x 3 11 12 13 14 15 16 17 18 19 20 21 z z z 1 0 0 0 1 x 3 8 9 10 11 12 13 14 15 z z z z z z 1 0 1 0 0 x 3 15 16 17 18 19 20 21 22 23 24 25 26 27 28 1 0 1 0 1 x 3 12 13 14 15 16 17 18 19 20 21 22 23 z z 1 1 0 0 0 0 1,2 11 12 13 14 15 16 17 18 19 20 21 z hh vh 1 1 0 0 0 1 1,2 11 12 13 14 15 16 17 18 19 20 z 21 hh vh 1 1 0 0 1 0 1,2 8 9 10 11 12 13 14 15 z z z z hh vh 1 1 0 0 1 1 1,2 8 9 10 11 12 13 14 z z z z 15 hh vh 1 1 1 0 0 1 1 15 16 17 18 19 20 21 22 23 24 25 28 hh vh 1 1 1 0 0 1 2 15 16 17 18 19 20 21 22 23 24 25 26 hh vh 1 1 1 0 0 0 1,2 15 16 17 18 19 20 21 22 23 24 25 26 hh vh 1 1 1 0 1 x 1,2 12 13 14 15 16 17 18 19 20 21 22 23 hh vh 1 0 0 1 0 0 0 12 13 14 15 16 17 18 19 20 24 25 26 hh vh 1 0 0 1 0 1 0 12 13 14 15 16 17 18 19 20 24 25 dh hh vh 1 0 0 1 1 0 0 9 10 11 12 13 14 15 16 17 z z z hh vh 1 0 0 1 1 1 0 9 10 11 12 13 14 15 16 17 z z dh hh vh bit settings mapped sync outputs db double mode bit dbl h hsync ( when dbl = 0) hv h/v encoding bit hven v vsync ( when dbl = 0) bw bws bit d de ( when dbl = 0) hb hibw bit hh hsync (high word, dbl = 1) cr pxl_crc bit vh vsync (high word, dbl = 1) de deen dh de (high word, dbl = 1) sc* hv_src (dec) hl hsync (low word, dbl = 1) x 1 or 0 vl vsync (low word, dbl = 1) bit color dl de (low word, dbl = 1) sync bits # serial bits output on frst word z zero output on second word zero * hv_src is automatically set by default. max96705 mode automatically sets hv_src to 0, 1, or 3 according to the other bit set - tings above. max96707 mode automatically sets hv_src to 0, 2, or 3 according to the other bit settings above. maxim integrated 64 www.maximintegrated.com max96706 14-bit gmsl deserializer with coax or stp cable input
control-channel interfaces i 2 c set i2csel = 1 to configure the control channel for i 2 c- to-i 2 c mode. in this mode, the control channel forwards i 2 c commands from the microcontroller side to the other side of the gmsl link. the remote device acts as an i 2 c master to the other peripherals connected to the remote side device. i 2 c-to-i 2 c mode uses clock stretching to hold the microcontroller until the data and the acknowledge/ no-acknowledge have been sent across the link. i 2 c bit rate the i 2 c interface accepts bit rates from 9.6kbps to 1mbps. the local i 2 c rate is set by the microcontroller. the remote i 2 c rate is set by the remote device. by default the control channel is set up for a 400kbps-to-i 2 c bit rate. program the i2c_mstbt and slv_sh bits (reg - ister 0x0d) to match the desired microcontroller i 2 c rate. software programming of the device addresses the serializer and deserializer have programmable device addresses. this allows multiple gmsl devices, along with i 2 c peripherals, to coexist on the same control channel. the serializer device address is in register 0x00 of each device, while the deserializer device address is in register 0x01 of each device. to change a device address, first write to the device whose address changes (register 0x00 of the serializer for serializer device address change, or register 0x01 of the deserializer for deserializer device address change). then write the same address into the corresponding register on the other device (register 0x00 of the deserializer for serializer device address change, or register 0x01 of the serializer for deserializer device address change). i 2 c address translation the device supports i 2 c address translation for up to two device addresses. use address translation to assign unique device addresses to peripherals with limited i 2 c addresses. source addresses (address to translate from) are stored in registers 0x09 and 0x0b. destination addresses (address to translate to) are stored in registers 0x0a and 0x0c. confguration blocking the device can block changes to its registers. set cfgblock to make all registers read only. once set, the registers remain blocked until the supplies are removed or until pwdnb is low. cascaded/parallel devices gmsl supports cascaded and parallel devices con - nected through i 2 c. when cascading or using parallel links, all i 2 c commands are forwarded to all links. each link attempts to hold the control channel until it receives an acknowledge/non-acknowledge from the remote side device. it is important to keep the control channel active between links in order to prevent timeout. if a link is unused, keep the control channel clear by turning on the configuration link, disconnecting the i 2 c lines, or power - ing down the unused device. dual c control most systems use a single microcontroller; however, cs can reside on each side simultaneously and trade off run - ning the control channel. contention occurs if both cs attempt to use the control channel at the same time. it is up to the user to prevent this contention by implementing a higher-level protocol. in addition, the control channel does not provide arbitration between i 2 c masters on both sides of the link. an acknowledge frame is not generated when communication fails due to contention. if communi - cation across the serial link is not required, the cs can disable the forward and reverse control channel using the fwdccen and revccen bits (0x04, d[1:0]) in the serializer/deserializer. communication across the serial link is stopped and contention between cs cannot occur. packet-based control-channel i 2 c packet-based control-channel i 2 c is not enabled by default. to enable packet-based i 2 c, set pktcc_en = 1 in the deserializer and wait 2ms. during this time, the deserializer automatically enables packet-based control channel in the serializer. the internal bit rate used by the packet control channel does not depend on the i 2 c bit rate used by the host c. the raw forward control channel bit rate is the same as pclk (e.g., 10mbps when f pclk is 10mhz). the raw reverse-channel bit rate is 850kbps typically (425kbps when him = 1). the packet length is 9 bits + the crc bit length, and affects the overall symbol rate. a larger crc bit length lowers the overall symbol rate. the latency of gpi/gpo transitions depend on the packet length. the latency of an i 2 c transmission across the control channel depends on both the incoming/outgoing scl rate and the control-channel symbol rate. sending a single byte from serializer to deserializer has an additional delay of 4 scl bit times + 1.5 symbols. sending a single byte from deserializer to serializer has an additional delay of 5 scl bit times + 1.5 symbols. maxim integrated 65 www.maximintegrated.com max96706 14-bit gmsl deserializer with coax or stp cable input
uart set i2csel = 0 to configure the control channel for uart or uart to i 2 c. in this mode, the control channel for - wards uart commands from the microcontroller side to the other side of the gmsl link. when inttype = 00, the remote device acts as an i 2 c master to the other periph - erals connected to the remote side device. uart-to-i 2 c mode does not support devices that use clock stretching. base mode in base mode, uart packets control the serializer, dese - rializer and attached peripherals. uart timing in base mode, the uart idles high (through a pullup resistor). each gmsl-uart byte consists of a start bit, 8 data bits, an even-parity bit and a stop bit ( figure 20 ). keep the idle time between bytes of the same uart packet to less than 4 bit times. the gmsl-uart protocol is listed in figure 21 . a write packet consists of a sync byte ( figure 22 ). device address byte, starting register address byte, number of bytes to write, and the data bytes. the slave device responds with an acknowledge byte ( figure 23 ) if the write was successful. a read pack - et consists of a sync byte, device address byte, starting register address byte, and number of bytes to read. the slave device responds with an acknowledge byte and the read data bytes. figure 20. gmsl-uart data format for base mode figure 21. gmsl-uart protocol for base mode figure 22. sync byte (0x79) figure 23. ack byte (0xc3) maxim integrated 66 start d0 d1 d2 d3 d4 d5 d6 d7 parity* stop 1 uart frame frame 1 frame 2 frame 3 *base mode uses even parity start stop start stop write data format sync reg addr number of bytes sync dev addr + r / w reg addr number of bytes byte 1 byte n ack byte n byte 1 ack master reads from slave read data format master writes to slave master writes to slave master reads from slave dev addr + r / w start d0 1 0 0 1 1 1 1 0 d1 d2 d3 d4 d5 d6 d7 parity stop start d0 1 1 0 0 0 0 1 1 d1 d2 d3 d4 d5 d6 d7 parity stop www.maximintegrated.com max96706 14-bit gmsl deserializer with coax or stp cable input
uart-to-i 2 c conversion when using the uart control channel, the remote-side device can communicate to i 2 c peripherals through uart-to-i 2 c conversion. set the inttype bits in the remote side device to "00" to activate uart-to-i 2 c conversion. the converted i 2 c bit rate is the same as the incoming uart bit rate. i 2 c peripherals must not use clock stretching in order to be compatible with uart- to-i 2 c conversion. there are two possible methods the devices use to convert uart to i 2 c. in the first method, i2cmethod = 0. the register address is sent with the i 2 c communica - tion ( figure 24 ). for devices that do not use a register address (such as the max7324) set i2cmethod = 1 and send a dummy byte in place of the register address ( figure 25 ). in this method, the remote device omits send - ing the register address. figure 24. format conversion between gmsl uart and i 2 c with register address (i2cmethod = 0) maxim integrated 67 11 sync frame register address number of bytes device id + wr data 0 dev id a 11 11 11 11 data n 11 11 s 1 1 1 ack frame 7 : master to slave 8 serializer/deserializer peripheral w 1 reg addr 8 a 1 1 8 1 11 sync frame register address number of bytes device id + rd 11 11 11 11 ack frame data 0 11 data n 11 uart-to-i 2 c conversion of write packet (i2cmethod = 0) uart-to-i 2 c conversion of read packet (i2cmethod = 0) s: start p: stop a: acknowledge : slave to master data 0 a data n a p dev id a s 1 1 7 w 1 dev id a s 1 1 7 r 1 data n p 1 8 a 1 data 0 8 a 1 reg addr 8 a 1 c serializer/deserializer c serializer/deserializer serializer/deserializer peripheral figure 25. format conversion between gmsl uart and i 2 c with register address (i2cmethod = 1) master to slave serializer/deserializer serializer/deserializer serializer/deserializer uart-to-i 2 c conversion of read packet (i2cmethod = 1) uart-to-i 2 c conversion of write packet (i2cmethod = 1) c serializer/deserializer c sync frame 11 11 11 11 11 11 11 11 11 11 11 11 11 11 device id + rd register address number of bytes sync frame device id + wr register address number of bytes data 0 data n ack frame ack frame data 0 data n data n a data 0 w a dev id s a p peripheral peripheral s 1 1 1 8 8 8 1 1 1 1 7 1 1 8 1 1 1 7 dev id r a a a p data 0 data n slave to master s: start p: stop a: acknowledge www.maximintegrated.com max96706 14-bit gmsl deserializer with coax or stp cable input
uart bypass mode in uart bypass mode, the control channel acts as a full-duplex 9.6kbps to 1mbps link that forwards uart commands across the serial link without responding to the packets themselves. set ms high to enter bypass mode (wait 1ms after setting bypass mode if the c is connected on the deserializer side). bypass uses bit rates from 9.6kbps to 1mbps. do not send a logic-low value longer than 100s when using the gpi/gpo functionality. device address the serdes have a 7-bit-long slave address stored in registers 0x00 and 0x01. the bit following a 7-bit slave address is the r/w bit, which is low for a write command and high for a read command. external inputs determine the default slave address as shown in table 8 . after start - up, a microcontroller can reprogram the slave address as needed. cable equalizer by default, the cable equalizer is enabled and set to adaptive mode. set aeq_en = 0 to switch to manual eq mode. eqtune determines the boost level in manual eq mode (see table 9 ). set en_eq = 0 to disable all equal - ization (manual or automatic). the auto-equalization level is determined during serial- link locking. set aeq_man_trg_req = 1 to re-trigger auto equalization. set aeq_per_mode = 1 to set up periodic aeq. errb output the deserializer has an open-drain errb output. this output asserts low whenever any of the following condi - tions occur: the number of detected errors exceeds the error thresholds during normal operation. read det_err, set auto-error reset, or re-lock the link to clear. exceeding the maximum number control channel retries. read max_rt_err to clear. measured eye width falls below a programmable threshold (40% by default). re-trigger an eye-width measurement (above the threshold) to clear. additional conditions that set errb (disabled by default) include: insufficient boost at maximum boost setting (set underbst_det_en = 1). retrigger the equalization calibration to clear. control-channel crc errors (set cc_crc_err_en = 1 to enable). read cc_crc_errcnt to clear. requires packet control channel (pktcc = 1). video line crc errors (turn on video-line crc to enable). read line_crc_err to clear. auto-error reset the default method to reset errors is to read the respec - tive error counter registers in the deserializer. auto-error reset clears the error counters det_err ~1s after err goes low. auto-error reset is disabled on power-up. enable auto-error reset through autorst. auto-error reset does not run when the device is in prbs test mode. table 8. default-device address d7 d6 d5 d4 d3 d2 d1 d0 1 add3 add2 1 add1 add0 0 r/w note: add[3:0] pin settings latched at power-up. *automatic eq is enabled by default. boost setting (manual and adaptive eq) typical boost gain at 750mhz (db) 0000 1.6 0001 2.1 0010 2.8 0011 3.5 0100 4.3 0101 5.2 0110 6.3 0111 7.3 1000 8.5 1001 9.7 power-up default for manual eq* 1010 11.0 1011 12.2 table 9. cable-equalizer boost levels maxim integrated 68 www.maximintegrated.com max96706 14-bit gmsl deserializer with coax or stp cable input
board layout power-supply circuits and bypassing the deserializer uses an avdd and dvdd of 1.7v to 1.9v. all inputs and outputs, except for the serial input, derive power from an iovdd of 1.7v to 3.6v that scales with iovdd. proper voltage-supply bypassing is essential for high-frequency circuit stability. high-frequency signals separate the lvcmos logic signals and cml/coax high - speed signals to prevent crosstalk. use a four-layer pcb with separate layers for power, ground, cml/coax, and lvcmos logic signals. layout stp pcb traces close to each other for a 100 differential characteristic imped - ance. the trace dimensions depend on the type of trace used (microstrip or stripline). note that two 50 pcb traces do not have 100 differential impedance when brought close togetherthe impedance goes down when the traces are brought closer. use a 50 trace for the single-ended output when driving coax. route the pcb traces for differential cml in parallel to maintain the dif - ferential characteristic impedance. avoid vias. keep pcb traces that make up a differential pair equal in length to avoid skew within the differential pair. esd protection esd tolerance is rated for human body model, iec 61000-4-2, and iso 10605. the iso 10605 and iec 61000-4-2 standards specify esd tolerance for electronic systems. the serial outputs are rated for iso 10605 esd protection and iec 61000-4-2 esd protection. all pins are tested for the human body model. the human body model discharge components are cs = 100pf and rd = 1.5k (figure 26). the iec 61000-4-2 discharge compo - nents are cs = 150pf and rd = 330 ( figure 27 ). the iso 10605 discharge components are cs = 330pf and rd = 2k ( figure 28 ). compatibility with other gmsl devices the device is designed to pair with the max96705? max96711 family of devices, but interoperates with any gmsl device. see table 10 for operating limitations. figure 26. human body model esd test circuit figure 27. iec 61000-4-2 contact discharge esd test circuit figure 28. iso 10605 contact discharge esd test circuit maxim integrated 69 storage capacitor high- voltage dc source device under test charge-current- limit resistor discharge resistance 1m? r d 1.5k? c s 100pf c s 150pf storage capacitor high- voltage dc source device under test charge-current- limit resistor discharge resistance r d 330? storage capacitor high- voltage dc source device under test charge-current- limit resistor discharge resistance r d 2k? c s 330pf www.maximintegrated.com max96706 14-bit gmsl deserializer with coax or stp cable input
device confguration and component selection internal input pulldowns the control and configuration inputs include a pulldown resistor to gnd. external pulldown resistors are not needed. multifunction inputs the device has several inputs/outputs that function both as a parallel input/output and as a configuration pin. on power-up, or when reverting from a power-down state, the pins act as configuration inputs. after latching the input state, the configuration inputs become parallel digi - tal input/outputs. connect a configuration input through a 30k resistor to iovdd to set a high level. leave the configuration input open to set a low level. i 2 c/uart pullup resistors the i 2 c and uart open-drain lines require a pullup resistor to provide a logic-high level. there are tradeoffs between power dissipation and speed, and a compromise may be required when choosing pullup resistor values. every device connected to the bus introduces some capacitance even when the device is not in operation. i 2 c specifies 300ns rise times (30% to 70%) for fast mode, which is defined for data rates up to 400kbps. see the i 2 c specifications in the i 2 c/uart port timing section in the ac electrical characteristics table for details. to meet the fast-mode rise-time requirement, choose the pullup resistors so that rise time t r = 0.85 x r pullup x c bus < 300ns. the waveforms are not recognized if the transition time becomes too slow. gmsl supports i 2 c/uart rates up to 1mbps (uart-to-i 2 c mode) and 400kbps (i 2 c-to- i 2 c mode). ac-coupling capacitors voltage droop and the digital sum variation (dsv) of trans - mitted symbols cause signal transitions to start from dif - ferent voltage levels. because the transition time is fixed, starting the signal transition from different voltage levels causes timing jitter. the time constant for an ac-coupled link needs to be chosen to reduce droop and jitter to an acceptable level. the rc network for an ac-coupled link consists of the cml/coax receiver termination resistor (r tr ), the cml/coax driver termination resistor (r td ), and the series ac-coupling capacitors (c). the rc time constant for four equal-value series capacitors is (c x (r td + r tr ))/4. r td and r tr are required to match the transmission line impedance (usually 100 differential, 50 single-ended). this leaves the capacitor selection to change the system time constant. use 0.2f or larger high-frequency surface-mount ceramic capacitors, with sufficient voltage rating to withstand a short to battery, to pass the lower-speed reverse control-channel signal. use capacitors with a case size less than 3.2mm x 1.6mm to have lower parasitic effects to the high-speed signal. cables and connectors interconnect for cml typically has a differential imped - ance of 100. use cables and connectors that have matched differential impedance to minimize impedance discontinuities. coax cables typically have a characteristic impedance of 50 (contact the factory for 75 operation). table 11 lists the suggested cables and connectors used in the gmsl link. deserializer feature gmsl serializer hsync/vsync encoding if feature not supported in the serializer, turn off in the deserializer. i 2 c-to-i 2 c if feature not supported in the serializer, use uart-to-i2c or uart-to-uart. packet control channel if feature not supported in the serializer, use legacy control channel. crc error detection if feature not supported in the serializer, turn off in the deserializer. double input if feature not supported in the serializer, data is output as a single word at half the input frequency. use crossbar switch to correct input mapping. coax if feature not supported in the serializer, connect unused serial input through 200nf and 50 in series to avdd, and set the reverse control-channel amplitude to 100mv. i 2 s encoding if supported in the serializer, disable i 2 s in the serializer high-bandwidth mode if feature not supported in the serializer, turn off in the deserializer. high-immunity mode if feature not supported in the serializer, turn off in the deserializer. table 10. feature compatibility maxim integrated 70 www.maximintegrated.com max96706 14-bit gmsl deserializer with coax or stp cable input
prbs the serializer includes a prbs pattern generator that works with bit-error verification in the deserializer. to run the prbs test, set prbsen = 1 (0x04, d5) in the deserializer, then in the serializer. to exit the prbs test, set prbsen = 0 (0x04, d5) in the serializer. the deserializer automatically ends prbs checking and sets the prbs_ok bit high. note that during prbs mode, the remote control channel is not available except to exit prbs mode if i2c_loc_ack=1; otherwise, the remote control channel is not available at all. to run the prbs with a 3gbps serdes, or when hibw = 1, first set the prbs_type bit = 0 in the max967xx. then set prbsen = 1 (0x04, d5) in the serializer, then in the deserializer. to exit the prbs test, set prbsen = 0 (0x04, d5) in the deserializer, then in the serializer. during prbs test, errb function changes to reflect prbs errors only. errb goes low when any prbs errors occur. errb goes high when the prbs error counter is reset when prbs_err is read. normal errb function resumes when exiting the prbs test. gpi/gpo gpo on the serializer follows gpi transitions on the deserializer. by default, the gpi-to-gpo delay is 0.35ms (max). keep the time between gpi transitions to a minimum 0.35ms. gpi_in the deserializer stores the gpi input state. gpo is low after power-up. the c can set gpo by writing to the set_gpo register bit. do not send a logic-low value on the deserializer rx/sda input (uart mode) longer than 100s in either base or bypass mode to ensure proper gpo/gpi functionality. fast detection of loss-of-lock a measure of link quality is the recovery time from loss of synchronization. the host can be quickly notified of loss-of-lock by connecting the deserializers lock output to the gpi input (when pktcc_en = 0). if other sources use the gpi input, such as a touch-screen controller, the c can implement a routine to distinguish between inter - rupts from loss-of-sync and normal interrupts. reverse control-channel communication does not require an active forward link to operate and accurately tracks the lock status of the gmsl link. lock asserts for video link only and not for the configuration link. providing a frame sync (camera applications) the gpi and gpo provide a simple solution for camera applications that require a frame sync signal from the ecu (e.g., surround-view systems). connect the ecu frame sync signal to the gpi input and connect the gpo output to the camera-frame sync input. gpi/gpo have a typical delay of 275s in legacy mode and 21s in packet mode (with 5-bit crc). skew between multiple gpi/gpo channels is 115s (max) in legacy mode and 21s (max) in packet mode. if a lower-skew signal is required in legacy mode, connect the cameras frame-sync input to one of the serializers gpios and use an i 2 c broadcast write command to change the gpio output state. this has a maximum skew of 1.5s, independent from the used i 2 c bit rate. in packet-based control-channel mode, set gpi_comp_en = 1 in both the serializer and the dese - rializer to turn on gpi/gpo compensation. this reduces the device-to-device skew to 0.35s. entering/exiting sleep mode the procedure for entering and exiting sleep mode depends on the location of the microcontroller, and the type of control-channel interface used. if wake-up from a remote-side (serializer-side) microcontroller is not needed or desired, set the dis_rwake bit = 1 to shut down remote wake-up for further power savings. legacy control channel when c is on the deserializer side, first put the serializer to sleep, or disable serialization. next, set sleep = 1 in deserializer. the device sleeps after 8ms. to wake up the device, send an arbitrary control-channel command to the deserializer (the device will not send an acknowledge), wait for 5ms for the chip to power up and then set sleep = 0 to make the wake-up permanent. when c is on the serializer side, set sleep = 1 in dese - rializer. next, disable serialization. the device sleeps after 8ms. to wake up the deserializer, reenable serialization. the deserializer wakes up and clears its sleep bit when it locks to the serializer. table 11. suggested connectors and cables for gmsl vendor connector cable type rosenberger 59s2ax-400a5-y dacar 302 coax rosenberger d4s10a-40ml5-z dacar 538 stp nissei gt11l-2s f-2wme awg28 stp jae mx38-ff a-bw-lxxxxx stp maxim integrated 71 www.maximintegrated.com max96706 14-bit gmsl deserializer with coax or stp cable input
packet-based control channel when c is on the deserializer side, first put the serializer to sleep, or disable serialization. next, set sleep = 1 in deserializer. the device sleeps after 8ms. to wake up the deserializer, send an arbitrary control-channel command to deserializer (the device will not send an acknowledge), wait for 5ms for the chip to power up, then set sleep = 0 to make the wake-up permanent. when c is on the serializer side, set sleep = 1 in deserializer. next, disable serialization in the serializer. the device sleeps after 8ms. to wake up the deserializer, reenable serialization. the deserializer wakes up and clear its sleep bit when it locks to the serializer. part number temp range pin-package max96706gtj+ -40c to +115c 32 tqfn-ep* max96706gtj+t -40c to +115c 32 tqfn-ep* max96706gtj/v+ -40c to +115c 32 tqfn-ep* max96706gtj/v+t -40c to +115c 32 tqfn-ep* /v denotes an automotive qualified product. +denotes a lead(pb)-free/rohs-compliant package. *ep = exposed pad. t = tape and reel. maxim integrated 72 ordering information typical application circuit conf1 conf0 rx/sda tx/scl/dbl out+ lccen dout[11:0] pclkout in+ in- gpi max96706 rx/sda tx/scl camera application lock max 96705 din [ 11 : 0 ] pclkin note : not all pullup / pulldown resistors are shown . see pin description for details . sda scl gpu ecu din [ 11 : 0 ] pclk din 14 / hs pclk din [ 11 : 0 ] camera hs i 2 c din 15 / vs vs sda scl ms/hven fsync lock out - 49.9 49.9k 49.9 45.3k 4.99k lmn0 errb err dout12/hs hs dout13/vs vs lfltb lflt i 2 csel = 1 , cx / tp = 1 www.maximintegrated.com max96706 14-bit gmsl deserializer with coax or stp cable input
revision number revision date description pages changed 0 4/16 initial release ? 2016 maxim integrated products, inc. 73 revision history maxim integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim integrated product. no circuit patent licenses are implied. maxim integrated reserves the right to change the circuitry and specifcations without notice at any time. the parametric values (min and max limits) shown in the electrical characteristics table are guaranteed. other parametric values quoted in this data sheet are provided for guidance. maxim integrated and the maxim integrated logo are trademarks of maxim integrated products, inc. max96706 14-bit gmsl deserializer with coax or stp cable input for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim integrateds website at www.maximintegrated.com.

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